timing.hh (4192:7accc6365bb9) | timing.hh (4471:4d86c4d096ad) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 52 unchanged lines hidden (view full) --- 61 62 protected: 63 Status _status; 64 65 Status status() const { return _status; } 66 67 Event *drainEvent; 68 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 52 unchanged lines hidden (view full) --- 61 62 protected: 63 Status _status; 64 65 Status status() const { return _status; } 66 67 Event *drainEvent; 68 |
69 Event *fetchEvent; 70 | |
71 private: 72 73 class CpuPort : public Port 74 { 75 protected: 76 TimingSimpleCPU *cpu; 77 Tick lat; 78 --- 115 unchanged lines hidden (view full) --- 194 195 template <class T> 196 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 197 198 void fetch(); 199 void completeIfetch(PacketPtr ); 200 void completeDataAccess(PacketPtr ); 201 void advanceInst(Fault fault); | 69 private: 70 71 class CpuPort : public Port 72 { 73 protected: 74 TimingSimpleCPU *cpu; 75 Tick lat; 76 --- 115 unchanged lines hidden (view full) --- 192 193 template <class T> 194 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 195 196 void fetch(); 197 void completeIfetch(PacketPtr ); 198 void completeDataAccess(PacketPtr ); 199 void advanceInst(Fault fault); |
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202 private: | 201 private: |
202 203 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 204 FetchEvent *fetchEvent; 205 |
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203 void completeDrain(); 204}; 205 206#endif // __CPU_SIMPLE_TIMING_HH__ | 206 void completeDrain(); 207}; 208 209#endif // __CPU_SIMPLE_TIMING_HH__ |