timing.hh (2901:f9a45473ab55) | timing.hh (2948:ae26cf37957c) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 60 unchanged lines hidden (view full) --- 69 Event *fetchEvent; 70 71 private: 72 73 class CpuPort : public Port 74 { 75 protected: 76 TimingSimpleCPU *cpu; | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 60 unchanged lines hidden (view full) --- 69 Event *fetchEvent; 70 71 private: 72 73 class CpuPort : public Port 74 { 75 protected: 76 TimingSimpleCPU *cpu; |
77 Tick lat; |
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77 78 public: 79 | 78 79 public: 80 |
80 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) 81 : Port(_name), cpu(_cpu) | 81 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 82 : Port(_name), cpu(_cpu), lat(_lat) |
82 { } 83 84 protected: 85 86 virtual Tick recvAtomic(Packet *pkt); 87 88 virtual void recvFunctional(Packet *pkt); 89 90 virtual void recvStatusChange(Status status); 91 92 virtual void getDeviceAddressRanges(AddrRangeList &resp, 93 AddrRangeList &snoop) 94 { resp.clear(); snoop.clear(); } | 83 { } 84 85 protected: 86 87 virtual Tick recvAtomic(Packet *pkt); 88 89 virtual void recvFunctional(Packet *pkt); 90 91 virtual void recvStatusChange(Status status); 92 93 virtual void getDeviceAddressRanges(AddrRangeList &resp, 94 AddrRangeList &snoop) 95 { resp.clear(); snoop.clear(); } |
96 97 struct TickEvent : public Event 98 { 99 Packet *pkt; 100 TimingSimpleCPU *cpu; 101 102 TickEvent(TimingSimpleCPU *_cpu) 103 :Event(&mainEventQueue), cpu(_cpu) {} 104 const char *description() { return "Timing CPU clock event"; } 105 void schedule(Packet *_pkt, Tick t); 106 }; 107 |
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95 }; 96 97 class IcachePort : public CpuPort 98 { 99 public: 100 | 108 }; 109 110 class IcachePort : public CpuPort 111 { 112 public: 113 |
101 IcachePort(TimingSimpleCPU *_cpu) 102 : CpuPort(_cpu->name() + "-iport", _cpu) | 114 IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 115 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) |
103 { } 104 105 protected: 106 107 virtual bool recvTiming(Packet *pkt); 108 109 virtual void recvRetry(); | 116 { } 117 118 protected: 119 120 virtual bool recvTiming(Packet *pkt); 121 122 virtual void recvRetry(); |
123 124 struct ITickEvent : public TickEvent 125 { 126 127 ITickEvent(TimingSimpleCPU *_cpu) 128 : TickEvent(_cpu) {} 129 void process(); 130 const char *description() { return "Timing CPU clock event"; } 131 }; 132 133 ITickEvent tickEvent; 134 |
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110 }; 111 112 class DcachePort : public CpuPort 113 { 114 public: 115 | 135 }; 136 137 class DcachePort : public CpuPort 138 { 139 public: 140 |
116 DcachePort(TimingSimpleCPU *_cpu) 117 : CpuPort(_cpu->name() + "-dport", _cpu) | 141 DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 142 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) |
118 { } 119 120 protected: 121 122 virtual bool recvTiming(Packet *pkt); 123 124 virtual void recvRetry(); | 143 { } 144 145 protected: 146 147 virtual bool recvTiming(Packet *pkt); 148 149 virtual void recvRetry(); |
150 151 struct DTickEvent : public TickEvent 152 { 153 DTickEvent(TimingSimpleCPU *_cpu) 154 : TickEvent(_cpu) {} 155 void process(); 156 const char *description() { return "Timing CPU clock event"; } 157 }; 158 159 DTickEvent tickEvent; 160 |
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125 }; 126 127 IcachePort icachePort; 128 DcachePort dcachePort; 129 130 Packet *ifetch_pkt; 131 Packet *dcache_pkt; 132 --- 31 unchanged lines hidden --- | 161 }; 162 163 IcachePort icachePort; 164 DcachePort dcachePort; 165 166 Packet *ifetch_pkt; 167 Packet *dcache_pkt; 168 --- 31 unchanged lines hidden --- |