timing.hh (2798:751e9170247e) timing.hh (2839:d5dd8a3cdea0)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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59 SwitchedOut
60 };
61
62 protected:
63 Status _status;
64
65 Status status() const { return _status; }
66
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 50 unchanged lines hidden (view full) ---

59 SwitchedOut
60 };
61
62 protected:
63 Status _status;
64
65 Status status() const { return _status; }
66
67 Event *quiesceEvent;
67 Event *drainEvent;
68
69 private:
70
71 class CpuPort : public Port
72 {
73 protected:
74 TimingSimpleCPU *cpu;
75

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128 Packet *ifetch_pkt;
129 Packet *dcache_pkt;
130
131 public:
132
133 virtual void serialize(std::ostream &os);
134 virtual void unserialize(Checkpoint *cp, const std::string &section);
135
68
69 private:
70
71 class CpuPort : public Port
72 {
73 protected:
74 TimingSimpleCPU *cpu;
75

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128 Packet *ifetch_pkt;
129 Packet *dcache_pkt;
130
131 public:
132
133 virtual void serialize(std::ostream &os);
134 virtual void unserialize(Checkpoint *cp, const std::string &section);
135
136 virtual bool quiesce(Event *quiesce_event);
136 virtual bool drain(Event *drain_event);
137 virtual void resume();
138 virtual void setMemoryMode(State new_mode);
139
140 void switchOut();
141 void takeOverFrom(BaseCPU *oldCPU);
142
143 virtual void activateContext(int thread_num, int delay);
144 virtual void suspendContext(int thread_num);

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149 template <class T>
150 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
151
152 void fetch();
153 void completeIfetch(Packet *);
154 void completeDataAccess(Packet *);
155 void advanceInst(Fault fault);
156 private:
137 virtual void resume();
138 virtual void setMemoryMode(State new_mode);
139
140 void switchOut();
141 void takeOverFrom(BaseCPU *oldCPU);
142
143 virtual void activateContext(int thread_num, int delay);
144 virtual void suspendContext(int thread_num);

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149 template <class T>
150 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
151
152 void fetch();
153 void completeIfetch(Packet *);
154 void completeDataAccess(Packet *);
155 void advanceInst(Fault fault);
156 private:
157 void completeQuiesce();
157 void completeDrain();
158};
159
160#endif // __CPU_SIMPLE_TIMING_HH__
158};
159
160#endif // __CPU_SIMPLE_TIMING_HH__