timing.hh (2632:1bb2f91485ea) timing.hh (2640:266b80dd5eca)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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66
67 class CpuPort : public Port
68 {
69 protected:
70 TimingSimpleCPU *cpu;
71
72 public:
73
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 57 unchanged lines hidden (view full) ---

66
67 class CpuPort : public Port
68 {
69 protected:
70 TimingSimpleCPU *cpu;
71
72 public:
73
74 CpuPort(TimingSimpleCPU *_cpu)
75 : cpu(_cpu)
74 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
75 : Port(_name), cpu(_cpu)
76 { }
77
78 protected:
79
80 virtual Tick recvAtomic(Packet *pkt);
81
82 virtual void recvFunctional(Packet *pkt);
83

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88 { resp.clear(); snoop.clear(); }
89 };
90
91 class IcachePort : public CpuPort
92 {
93 public:
94
95 IcachePort(TimingSimpleCPU *_cpu)
76 { }
77
78 protected:
79
80 virtual Tick recvAtomic(Packet *pkt);
81
82 virtual void recvFunctional(Packet *pkt);
83

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88 { resp.clear(); snoop.clear(); }
89 };
90
91 class IcachePort : public CpuPort
92 {
93 public:
94
95 IcachePort(TimingSimpleCPU *_cpu)
96 : CpuPort(_cpu)
96 : CpuPort(_cpu->name() + "-iport", _cpu)
97 { }
98
99 protected:
100
101 virtual bool recvTiming(Packet *pkt);
102
103 virtual Packet *recvRetry();
104 };
105
106 class DcachePort : public CpuPort
107 {
108 public:
109
110 DcachePort(TimingSimpleCPU *_cpu)
97 { }
98
99 protected:
100
101 virtual bool recvTiming(Packet *pkt);
102
103 virtual Packet *recvRetry();
104 };
105
106 class DcachePort : public CpuPort
107 {
108 public:
109
110 DcachePort(TimingSimpleCPU *_cpu)
111 : CpuPort(_cpu)
111 : CpuPort(_cpu->name() + "-dport", _cpu)
112 { }
113
114 protected:
115
116 virtual bool recvTiming(Packet *pkt);
117
118 virtual Packet *recvRetry();
119 };

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113
114 protected:
115
116 virtual bool recvTiming(Packet *pkt);
117
118 virtual Packet *recvRetry();
119 };

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