| timing.hh (14085:0075b0d29d55) | timing.hh (14198:9c2f67392409) |
|---|---|
| 1/* 2 * Copyright (c) 2012-2013,2015,2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 250 unchanged lines hidden (view full) --- 259 PacketPtr ifetch_pkt; 260 PacketPtr dcache_pkt; 261 262 Cycles previousCycle; 263 264 protected: 265 266 /** Return a reference to the data port. */ | 1/* 2 * Copyright (c) 2012-2013,2015,2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 250 unchanged lines hidden (view full) --- 259 PacketPtr ifetch_pkt; 260 PacketPtr dcache_pkt; 261 262 Cycles previousCycle; 263 264 protected: 265 266 /** Return a reference to the data port. */ |
| 267 MasterPort &getDataPort() override { return dcachePort; } | 267 Port &getDataPort() override { return dcachePort; } |
| 268 269 /** Return a reference to the instruction port. */ | 268 269 /** Return a reference to the instruction port. */ |
| 270 MasterPort &getInstPort() override { return icachePort; } | 270 Port &getInstPort() override { return icachePort; } |
| 271 272 public: 273 274 DrainState drain() override; 275 void drainResume() override; 276 277 void switchOut() override; 278 void takeOverFrom(BaseCPU *oldCPU) override; --- 91 unchanged lines hidden --- | 271 272 public: 273 274 DrainState drain() override; 275 void drainResume() override; 276 277 void switchOut() override; 278 void takeOverFrom(BaseCPU *oldCPU) override; --- 91 unchanged lines hidden --- |