timing.hh (12085:de78ea63e0ca) timing.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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119 void
120 markDelayed()
121 {
122 assert(cpu->_status == BaseSimpleCPU::Running);
123 cpu->_status = ITBWaitResponse;
124 }
125
126 void
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 110 unchanged lines hidden (view full) ---

119 void
120 markDelayed()
121 {
122 assert(cpu->_status == BaseSimpleCPU::Running);
123 cpu->_status = ITBWaitResponse;
124 }
125
126 void
127 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
127 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
128 BaseTLB::Mode mode)
129 {
130 cpu->sendFetch(fault, req, tc);
131 }
132 };
133 FetchTranslation fetchTranslation;
134
135 void threadSnoop(PacketPtr pkt, ThreadID sender);
128 BaseTLB::Mode mode)
129 {
130 cpu->sendFetch(fault, req, tc);
131 }
132 };
133 FetchTranslation fetchTranslation;
134
135 void threadSnoop(PacketPtr pkt, ThreadID sender);
136 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
137 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
136 void sendData(const RequestPtr &req,
137 uint8_t *data, uint64_t *res, bool read);
138 void sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
139 const RequestPtr &req,
138 uint8_t *data, bool read);
139
140 void translationFault(const Fault &fault);
141
140 uint8_t *data, bool read);
141
142 void translationFault(const Fault &fault);
143
142 PacketPtr buildPacket(RequestPtr req, bool read);
144 PacketPtr buildPacket(const RequestPtr &req, bool read);
143 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
145 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
144 RequestPtr req1, RequestPtr req2, RequestPtr req,
146 const RequestPtr &req1, const RequestPtr &req2,
147 const RequestPtr &req,
145 uint8_t *data, bool read);
146
147 bool handleReadPacket(PacketPtr pkt);
148 // This function always implicitly uses dcache_pkt.
149 bool handleWritePacket();
150
151 /**
152 * A TimingCPUPort overrides the default behaviour of the

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284
285 Fault initiateMemRead(Addr addr, unsigned size,
286 Request::Flags flags) override;
287
288 Fault writeMem(uint8_t *data, unsigned size,
289 Addr addr, Request::Flags flags, uint64_t *res) override;
290
291 void fetch();
148 uint8_t *data, bool read);
149
150 bool handleReadPacket(PacketPtr pkt);
151 // This function always implicitly uses dcache_pkt.
152 bool handleWritePacket();
153
154 /**
155 * A TimingCPUPort overrides the default behaviour of the

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287
288 Fault initiateMemRead(Addr addr, unsigned size,
289 Request::Flags flags) override;
290
291 Fault writeMem(uint8_t *data, unsigned size,
292 Addr addr, Request::Flags flags, uint64_t *res) override;
293
294 void fetch();
292 void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
295 void sendFetch(const Fault &fault,
296 const RequestPtr &req, ThreadContext *tc);
293 void completeIfetch(PacketPtr );
294 void completeDataAccess(PacketPtr pkt);
295 void advanceInst(const Fault &fault);
296
297 /** This function is used by the page table walker to determine if it could
298 * translate the a pending request or if the underlying request has been
299 * squashed. This always returns false for the simple timing CPU as it never
300 * executes any instructions speculatively.

--- 61 unchanged lines hidden --- 		297 void completeIfetch(PacketPtr );
298 void completeDataAccess(PacketPtr pkt);
299 void advanceInst(const Fault &fault);
300
301 /** This function is used by the page table walker to determine if it could
302 * translate the a pending request or if the underlying request has been
303 * squashed. This always returns false for the simple timing CPU as it never
304 * executes any instructions speculatively.

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