timing.hh (11168:f98eb2da15a4) timing.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50
51class TimingSimpleCPU : public BaseSimpleCPU
52{
53 public:
54
55 TimingSimpleCPU(TimingSimpleCPUParams * params);
56 virtual ~TimingSimpleCPU();
57
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50
51class TimingSimpleCPU : public BaseSimpleCPU
52{
53 public:
54
55 TimingSimpleCPU(TimingSimpleCPUParams * params);
56 virtual ~TimingSimpleCPU();
57
58 virtual void init();
58 void init() override;
59
60 private:
61
62 /*
63 * If an access needs to be broken into fragments, currently at most two,
64 * the the following two classes are used as the sender state of the
65 * packets so the CPU can keep track of everything. In the main packet
66 * sender state, there's an array with a spot for each fragment. If a

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260 PacketPtr ifetch_pkt;
261 PacketPtr dcache_pkt;
262
263 Cycles previousCycle;
264
265 protected:
266
267 /** Return a reference to the data port. */
59
60 private:
61
62 /*
63 * If an access needs to be broken into fragments, currently at most two,
64 * the the following two classes are used as the sender state of the
65 * packets so the CPU can keep track of everything. In the main packet
66 * sender state, there's an array with a spot for each fragment. If a

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260 PacketPtr ifetch_pkt;
261 PacketPtr dcache_pkt;
262
263 Cycles previousCycle;
264
265 protected:
266
267 /** Return a reference to the data port. */
268 virtual MasterPort &getDataPort() { return dcachePort; }
268 MasterPort &getDataPort() override { return dcachePort; }
269
270 /** Return a reference to the instruction port. */
269
270 /** Return a reference to the instruction port. */
271 virtual MasterPort &getInstPort() { return icachePort; }
271 MasterPort &getInstPort() override { return icachePort; }
272
273 public:
274
275 DrainState drain() override;
276 void drainResume() override;
277
272
273 public:
274
275 DrainState drain() override;
276 void drainResume() override;
277
278 void switchOut();
279 void takeOverFrom(BaseCPU *oldCPU);
278 void switchOut() override;
279 void takeOverFrom(BaseCPU *oldCPU) override;
280
280
281 void verifyMemoryMode() const;
281 void verifyMemoryMode() const override;
282
282
283 virtual void activateContext(ThreadID thread_num);
284 virtual void suspendContext(ThreadID thread_num);
283 void activateContext(ThreadID thread_num) override;
284 void suspendContext(ThreadID thread_num) override;
285
285
286 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
286 Fault readMem(Addr addr, uint8_t *data, unsigned size,
287 unsigned flags) override;
287
288 Fault writeMem(uint8_t *data, unsigned size,
288
289 Fault writeMem(uint8_t *data, unsigned size,
289 Addr addr, unsigned flags, uint64_t *res);
290 Addr addr, unsigned flags, uint64_t *res) override;
290
291 void fetch();
292 void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
293 void completeIfetch(PacketPtr );
294 void completeDataAccess(PacketPtr pkt);
295 void advanceInst(const Fault &fault);
296
297 /** This function is used by the page table walker to determine if it could

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292 void fetch();
293 void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
294 void completeIfetch(PacketPtr );
295 void completeDataAccess(PacketPtr pkt);
296 void advanceInst(const Fault &fault);
297
298 /** This function is used by the page table walker to determine if it could

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