timing.hh (11148:1bc3d93c7eaa) timing.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 258 unchanged lines hidden (view full) ---

267 /** Return a reference to the data port. */
268 virtual MasterPort &getDataPort() { return dcachePort; }
269
270 /** Return a reference to the instruction port. */
271 virtual MasterPort &getInstPort() { return icachePort; }
272
273 public:
274
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 258 unchanged lines hidden (view full) ---

267 /** Return a reference to the data port. */
268 virtual MasterPort &getDataPort() { return dcachePort; }
269
270 /** Return a reference to the instruction port. */
271 virtual MasterPort &getInstPort() { return icachePort; }
272
273 public:
274
275 DrainState drain() M5_ATTR_OVERRIDE;
276 void drainResume() M5_ATTR_OVERRIDE;
275 DrainState drain() override;
276 void drainResume() override;
277
278 void switchOut();
279 void takeOverFrom(BaseCPU *oldCPU);
280
281 void verifyMemoryMode() const;
282
283 virtual void activateContext(ThreadID thread_num);
284 virtual void suspendContext(ThreadID thread_num);

--- 78 unchanged lines hidden --- 		277
278 void switchOut();
279 void takeOverFrom(BaseCPU *oldCPU);
280
281 void verifyMemoryMode() const;
282
283 virtual void activateContext(ThreadID thread_num);
284 virtual void suspendContext(ThreadID thread_num);

--- 78 unchanged lines hidden ---