timing.hh (10407:a9023811bf9e) timing.hh (10464:2a0fe8bca031)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 231 unchanged lines hidden (view full) ---

240 void process();
241 const char *description() const { return "Timing CPU dcache tick"; }
242 };
243
244 DTickEvent tickEvent;
245
246 };
247
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 231 unchanged lines hidden (view full) ---

240 void process();
241 const char *description() const { return "Timing CPU dcache tick"; }
242 };
243
244 DTickEvent tickEvent;
245
246 };
247
248 void updateCycleCounts();
249
248 IcachePort icachePort;
249 DcachePort dcachePort;
250
251 PacketPtr ifetch_pkt;
252 PacketPtr dcache_pkt;
253
250 IcachePort icachePort;
251 DcachePort dcachePort;
252
253 PacketPtr ifetch_pkt;
254 PacketPtr dcache_pkt;
255
254 Tick previousCycle;
256 Cycles previousCycle;
255
256 protected:
257
258 /** Return a reference to the data port. */
259 virtual MasterPort &getDataPort() { return dcachePort; }
260
261 /** Return a reference to the instruction port. */
262 virtual MasterPort &getInstPort() { return icachePort; }

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258 protected:
259
260 /** Return a reference to the data port. */
261 virtual MasterPort &getDataPort() { return dcachePort; }
262
263 /** Return a reference to the instruction port. */
264 virtual MasterPort &getInstPort() { return icachePort; }

--- 94 unchanged lines hidden ---