timing.hh (10030:b531e328342d) timing.hh (10379:c00f6d7e2681)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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118 void
119 markDelayed()
120 {
121 assert(cpu->_status == BaseSimpleCPU::Running);
122 cpu->_status = ITBWaitResponse;
123 }
124
125 void
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 109 unchanged lines hidden (view full) ---

118 void
119 markDelayed()
120 {
121 assert(cpu->_status == BaseSimpleCPU::Running);
122 cpu->_status = ITBWaitResponse;
123 }
124
125 void
126 finish(Fault fault, RequestPtr req, ThreadContext *tc,
126 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
127 BaseTLB::Mode mode)
128 {
129 cpu->sendFetch(fault, req, tc);
130 }
131 };
132 FetchTranslation fetchTranslation;
133
134 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
135 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
136 uint8_t *data, bool read);
137
127 BaseTLB::Mode mode)
128 {
129 cpu->sendFetch(fault, req, tc);
130 }
131 };
132 FetchTranslation fetchTranslation;
133
134 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
135 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
136 uint8_t *data, bool read);
137
138 void translationFault(Fault fault);
138 void translationFault(const Fault &fault);
139
140 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
141 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
142 RequestPtr req1, RequestPtr req2, RequestPtr req,
143 uint8_t *data, bool read);
144
145 bool handleReadPacket(PacketPtr pkt);
146 // This function always implicitly uses dcache_pkt.

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275 virtual void suspendContext(ThreadID thread_num);
276
277 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
278
279 Fault writeMem(uint8_t *data, unsigned size,
280 Addr addr, unsigned flags, uint64_t *res);
281
282 void fetch();
139
140 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
141 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
142 RequestPtr req1, RequestPtr req2, RequestPtr req,
143 uint8_t *data, bool read);
144
145 bool handleReadPacket(PacketPtr pkt);
146 // This function always implicitly uses dcache_pkt.

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275 virtual void suspendContext(ThreadID thread_num);
276
277 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
278
279 Fault writeMem(uint8_t *data, unsigned size,
280 Addr addr, unsigned flags, uint64_t *res);
281
282 void fetch();
283 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
283 void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
284 void completeIfetch(PacketPtr );
285 void completeDataAccess(PacketPtr pkt);
284 void completeIfetch(PacketPtr );
285 void completeDataAccess(PacketPtr pkt);
286 void advanceInst(Fault fault);
286 void advanceInst(const Fault &fault);
287
288 /** This function is used by the page table walker to determine if it could
289 * translate the a pending request or if the underlying request has been
290 * squashed. This always returns false for the simple timing CPU as it never
291 * executes any instructions speculatively.
292 * @ return Is the current instruction squashed?
293 */
294 bool isSquashed() const { return false; }

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288 /** This function is used by the page table walker to determine if it could
289 * translate the a pending request or if the underlying request has been
290 * squashed. This always returns false for the simple timing CPU as it never
291 * executes any instructions speculatively.
292 * @ return Is the current instruction squashed?
293 */
294 bool isSquashed() const { return false; }

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