1/* |
2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 29 unchanged lines hidden (view full) --- 51{ 52 public: 53 54 TimingSimpleCPU(TimingSimpleCPUParams * params); 55 virtual ~TimingSimpleCPU(); 56 57 virtual void init(); 58 |
59 private: 60 61 /* 62 * If an access needs to be broken into fragments, currently at most two, 63 * the the following two classes are used as the sender state of the 64 * packets so the CPU can keep track of everything. In the main packet 65 * sender state, there's an array with a spot for each fragment. If a 66 * fragment has already been accepted by the CPU, aka isn't waiting for --- 183 unchanged lines hidden (view full) --- 250 /** Return a reference to the data port. */ 251 virtual CpuPort &getDataPort() { return dcachePort; } 252 253 /** Return a reference to the instruction port. */ 254 virtual CpuPort &getInstPort() { return icachePort; } 255 256 public: 257 |
258 unsigned int drain(DrainManager *drain_manager); 259 void drainResume(); 260 261 void switchOut(); 262 void takeOverFrom(BaseCPU *oldCPU); 263 264 virtual void activateContext(ThreadID thread_num, Cycles delay); 265 virtual void suspendContext(ThreadID thread_num); --- 37 unchanged lines hidden (view full) --- 303 struct IprEvent : Event { 304 Packet *pkt; 305 TimingSimpleCPU *cpu; 306 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 307 virtual void process(); 308 virtual const char *description() const; 309 }; 310 |
311 /** 312 * Check if a system is in a drained state. 313 * 314 * We need to drain if: 315 * <ul> 316 * <li>We are in the middle of a microcode sequence as some CPUs 317 * (e.g., HW accelerated CPUs) can't be started in the middle 318 * of a gem5 microcode sequence. 319 * 320 * <li>Stay at PC is true. 321 * </ul> 322 */ 323 bool isDrained() { 324 return microPC() == 0 && 325 !stayAtPC; 326 } 327 328 /** 329 * Try to complete a drain request. 330 * 331 * @returns true if the CPU is drained, false otherwise. 332 */ 333 bool tryCompleteDrain(); 334 335 /** 336 * Drain manager to use when signaling drain completion 337 * 338 * This pointer is non-NULL when draining and NULL otherwise. 339 */ 340 DrainManager *drainManager; |
341}; 342 343#endif // __CPU_SIMPLE_TIMING_HH__ |