1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 156 unchanged lines hidden (view full) --- 165 PacketPtr pkt; 166 TimingSimpleCPU *cpu; 167 168 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} 169 const char *description() const { return "Timing CPU tick"; } 170 void schedule(PacketPtr _pkt, Tick t); 171 }; 172 |
173 EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent; |
174 }; 175 176 class IcachePort : public TimingCPUPort 177 { 178 public: 179 180 IcachePort(TimingSimpleCPU *_cpu) 181 : TimingCPUPort(_cpu->name() + "-iport", _cpu), --- 118 unchanged lines hidden --- |