1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 123 unchanged lines hidden (view full) --- 132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 133 RequestPtr req1, RequestPtr req2, RequestPtr req, 134 uint8_t *data, bool read); 135 136 bool handleReadPacket(PacketPtr pkt); 137 // This function always implicitly uses dcache_pkt. 138 bool handleWritePacket(); 139 |
140 /** 141 * A TimingCPUPort overrides the default behaviour of the 142 * recvTiming and recvRetry and implements events for the 143 * scheduling of handling of incoming packets in the following 144 * cycle. 145 */ 146 class TimingCPUPort : public CpuPort |
147 { |
148 public: 149 |
150 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) 151 : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this) |
152 { } 153 |
154 protected: 155 |
156 TimingSimpleCPU* cpu; |
157 |
158 struct TickEvent : public Event 159 { 160 PacketPtr pkt; 161 TimingSimpleCPU *cpu; 162 CpuPort *port; 163 |
164 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} |
165 const char *description() const { return "Timing CPU tick"; } 166 void schedule(PacketPtr _pkt, Tick t); 167 }; 168 169 EventWrapper<Port, &Port::sendRetry> retryEvent; 170 }; 171 |
172 class IcachePort : public TimingCPUPort |
173 { 174 public: 175 |
176 IcachePort(TimingSimpleCPU *_cpu) 177 : TimingCPUPort(_cpu->name() + "-iport", _cpu), 178 tickEvent(_cpu) |
179 { } 180 181 protected: 182 183 virtual bool recvTiming(PacketPtr pkt); 184 185 virtual void recvRetry(); 186 --- 5 unchanged lines hidden (view full) --- 192 void process(); 193 const char *description() const { return "Timing CPU icache tick"; } 194 }; 195 196 ITickEvent tickEvent; 197 198 }; 199 |
200 class DcachePort : public TimingCPUPort |
201 { 202 public: 203 |
204 DcachePort(TimingSimpleCPU *_cpu) 205 : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu) |
206 { } 207 208 protected: 209 210 virtual bool recvTiming(PacketPtr pkt); 211 212 virtual void recvRetry(); 213 --- 76 unchanged lines hidden --- |