1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 175 unchanged lines hidden (view full) --- 184 void takeOverFrom(BaseCPU *oldCPU); 185 186 virtual void activateContext(int thread_num, int delay); 187 virtual void suspendContext(int thread_num); 188 189 template <class T> 190 Fault read(Addr addr, T &data, unsigned flags); 191 |
192 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 193 int size, unsigned flags); 194 |
195 template <class T> 196 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 197 |
198 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 199 int size, unsigned flags); 200 |
201 void fetch(); 202 void completeIfetch(PacketPtr ); 203 void completeDataAccess(PacketPtr ); 204 void advanceInst(Fault fault); 205 206 private: 207 208 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; --- 14 unchanged lines hidden --- |