140c140,146
< class CpuPort : public Port
---
> /**
> * A TimingCPUPort overrides the default behaviour of the
> * recvTiming and recvRetry and implements events for the
> * scheduling of handling of incoming packets in the following
> * cycle.
> */
> class TimingCPUPort : public CpuPort
142,145d147
< protected:
< TimingSimpleCPU *cpu;
< Tick lat;
<
148,149c150,151
< CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
< : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
---
> TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
> : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
152,153d153
< bool snoopRangeSent;
<
156c156
< virtual Tick recvAtomic(PacketPtr pkt);
---
> TimingSimpleCPU* cpu;
158,165d157
< virtual void recvFunctional(PacketPtr pkt);
<
< virtual void recvStatusChange(Status status);
<
< virtual void getDeviceAddressRanges(AddrRangeList &resp,
< bool &snoop)
< { resp.clear(); snoop = false; }
<
172c164
< TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
---
> TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
180c172
< class IcachePort : public CpuPort
---
> class IcachePort : public TimingCPUPort
184,185c176,178
< IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
< : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
---
> IcachePort(TimingSimpleCPU *_cpu)
> : TimingCPUPort(_cpu->name() + "-iport", _cpu),
> tickEvent(_cpu)
207c200
< class DcachePort : public CpuPort
---
> class DcachePort : public TimingCPUPort
211,212c204,205
< DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
< : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
---
> DcachePort(TimingSimpleCPU *_cpu)
> : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)