1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35#include "cpu/translation.hh"
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
47 public:
48 Event *drainEvent;
49
50 private:
51
52 /*
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for
58 * a retry, it's pointer is NULL. After each fragment has successfully
59 * been processed, the "outstanding" counter is decremented. Once the
60 * count is zero, the entire larger access is complete.
61 */
62 class SplitMainSenderState : public Packet::SenderState
63 {
64 public:
65 int outstanding;
66 PacketPtr fragments[2];
67
68 int
69 getPendingFragment()
70 {
71 if (fragments[0]) {
72 return 0;
73 } else if (fragments[1]) {
74 return 1;
75 } else {
76 return -1;
77 }
78 }
79 };
80
81 class SplitFragmentSenderState : public Packet::SenderState
82 {
83 public:
84 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85 bigPkt(_bigPkt), index(_index)
86 {}
87 PacketPtr bigPkt;
88 int index;
89
90 void
91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
99 class FetchTranslation : public BaseTLB::Translation
100 {
101 protected:
102 TimingSimpleCPU *cpu;
103
104 public:
105 FetchTranslation(TimingSimpleCPU *_cpu)
106 : cpu(_cpu)
107 {}
108
109 void
110 markDelayed()
111 {
112 assert(cpu->_status == Running);
113 cpu->_status = ITBWaitResponse;
114 }
115
116 void
117 finish(Fault fault, RequestPtr req, ThreadContext *tc,
118 BaseTLB::Mode mode)
119 {
120 cpu->sendFetch(fault, req, tc);
121 }
122 };
123 FetchTranslation fetchTranslation;
124
125 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
126 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
127 uint8_t *data, bool read);
128
129 void translationFault(Fault fault);
130
131 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
140 /**
141 * A TimingCPUPort overrides the default behaviour of the
142 * recvTiming and recvRetry and implements events for the
143 * scheduling of handling of incoming packets in the following
144 * cycle.
145 */
146 class TimingCPUPort : public CpuPort
147 {
148 public:
149
150 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
151 : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
152 { }
153
154 protected:
155
156 /**
157 * Snooping a coherence request, do nothing.
158 */
159 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
160
161 TimingSimpleCPU* cpu;
162
163 struct TickEvent : public Event
164 {
165 PacketPtr pkt;
166 TimingSimpleCPU *cpu;
167
168 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
169 const char *description() const { return "Timing CPU tick"; }
170 void schedule(PacketPtr _pkt, Tick t);
171 };
172
173 EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent;
174 };
175
176 class IcachePort : public TimingCPUPort
177 {
178 public:
179
180 IcachePort(TimingSimpleCPU *_cpu)
181 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
182 tickEvent(_cpu)
183 { }
184
185 protected:
186
187 virtual bool recvTimingResp(PacketPtr pkt);
188
189 virtual void recvRetry();
190
191 struct ITickEvent : public TickEvent
192 {
193
194 ITickEvent(TimingSimpleCPU *_cpu)
195 : TickEvent(_cpu) {}
196 void process();
197 const char *description() const { return "Timing CPU icache tick"; }
198 };
199
200 ITickEvent tickEvent;
201
202 };
203
204 class DcachePort : public TimingCPUPort
205 {
206 public:
207
208 DcachePort(TimingSimpleCPU *_cpu)
209 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
210 tickEvent(_cpu)
211 { }
212
213 protected:
214
215 virtual bool recvTimingResp(PacketPtr pkt);
216
217 virtual void recvRetry();
218
219 struct DTickEvent : public TickEvent
220 {
221 DTickEvent(TimingSimpleCPU *_cpu)
222 : TickEvent(_cpu) {}
223 void process();
224 const char *description() const { return "Timing CPU dcache tick"; }
225 };
226
227 DTickEvent tickEvent;
228
229 };
230
231 IcachePort icachePort;
232 DcachePort dcachePort;
233
234 PacketPtr ifetch_pkt;
235 PacketPtr dcache_pkt;
236
237 Tick previousCycle;
238
239 protected:
240
241 /** Return a reference to the data port. */
242 virtual CpuPort &getDataPort() { return dcachePort; }
243
244 /** Return a reference to the instruction port. */
245 virtual CpuPort &getInstPort() { return icachePort; }
246
247 public:
248
249 virtual void serialize(std::ostream &os);
250 virtual void unserialize(Checkpoint *cp, const std::string §ion);
251
252 virtual unsigned int drain(Event *drain_event);
253 virtual void resume();
254
255 void switchOut();
256 void takeOverFrom(BaseCPU *oldCPU);
257
258 virtual void activateContext(ThreadID thread_num, Cycles delay);
259 virtual void suspendContext(ThreadID thread_num);
260
261 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
262
263 Fault writeMem(uint8_t *data, unsigned size,
264 Addr addr, unsigned flags, uint64_t *res);
265
266 void fetch();
267 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
268 void completeIfetch(PacketPtr );
269 void completeDataAccess(PacketPtr pkt);
270 void advanceInst(Fault fault);
271
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35#include "cpu/translation.hh"
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
47 public:
48 Event *drainEvent;
49
50 private:
51
52 /*
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for
58 * a retry, it's pointer is NULL. After each fragment has successfully
59 * been processed, the "outstanding" counter is decremented. Once the
60 * count is zero, the entire larger access is complete.
61 */
62 class SplitMainSenderState : public Packet::SenderState
63 {
64 public:
65 int outstanding;
66 PacketPtr fragments[2];
67
68 int
69 getPendingFragment()
70 {
71 if (fragments[0]) {
72 return 0;
73 } else if (fragments[1]) {
74 return 1;
75 } else {
76 return -1;
77 }
78 }
79 };
80
81 class SplitFragmentSenderState : public Packet::SenderState
82 {
83 public:
84 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85 bigPkt(_bigPkt), index(_index)
86 {}
87 PacketPtr bigPkt;
88 int index;
89
90 void
91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
99 class FetchTranslation : public BaseTLB::Translation
100 {
101 protected:
102 TimingSimpleCPU *cpu;
103
104 public:
105 FetchTranslation(TimingSimpleCPU *_cpu)
106 : cpu(_cpu)
107 {}
108
109 void
110 markDelayed()
111 {
112 assert(cpu->_status == Running);
113 cpu->_status = ITBWaitResponse;
114 }
115
116 void
117 finish(Fault fault, RequestPtr req, ThreadContext *tc,
118 BaseTLB::Mode mode)
119 {
120 cpu->sendFetch(fault, req, tc);
121 }
122 };
123 FetchTranslation fetchTranslation;
124
125 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
126 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
127 uint8_t *data, bool read);
128
129 void translationFault(Fault fault);
130
131 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
140 /**
141 * A TimingCPUPort overrides the default behaviour of the
142 * recvTiming and recvRetry and implements events for the
143 * scheduling of handling of incoming packets in the following
144 * cycle.
145 */
146 class TimingCPUPort : public CpuPort
147 {
148 public:
149
150 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
151 : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
152 { }
153
154 protected:
155
156 /**
157 * Snooping a coherence request, do nothing.
158 */
159 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
160
161 TimingSimpleCPU* cpu;
162
163 struct TickEvent : public Event
164 {
165 PacketPtr pkt;
166 TimingSimpleCPU *cpu;
167
168 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
169 const char *description() const { return "Timing CPU tick"; }
170 void schedule(PacketPtr _pkt, Tick t);
171 };
172
173 EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent;
174 };
175
176 class IcachePort : public TimingCPUPort
177 {
178 public:
179
180 IcachePort(TimingSimpleCPU *_cpu)
181 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
182 tickEvent(_cpu)
183 { }
184
185 protected:
186
187 virtual bool recvTimingResp(PacketPtr pkt);
188
189 virtual void recvRetry();
190
191 struct ITickEvent : public TickEvent
192 {
193
194 ITickEvent(TimingSimpleCPU *_cpu)
195 : TickEvent(_cpu) {}
196 void process();
197 const char *description() const { return "Timing CPU icache tick"; }
198 };
199
200 ITickEvent tickEvent;
201
202 };
203
204 class DcachePort : public TimingCPUPort
205 {
206 public:
207
208 DcachePort(TimingSimpleCPU *_cpu)
209 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
210 tickEvent(_cpu)
211 { }
212
213 protected:
214
215 virtual bool recvTimingResp(PacketPtr pkt);
216
217 virtual void recvRetry();
218
219 struct DTickEvent : public TickEvent
220 {
221 DTickEvent(TimingSimpleCPU *_cpu)
222 : TickEvent(_cpu) {}
223 void process();
224 const char *description() const { return "Timing CPU dcache tick"; }
225 };
226
227 DTickEvent tickEvent;
228
229 };
230
231 IcachePort icachePort;
232 DcachePort dcachePort;
233
234 PacketPtr ifetch_pkt;
235 PacketPtr dcache_pkt;
236
237 Tick previousCycle;
238
239 protected:
240
241 /** Return a reference to the data port. */
242 virtual CpuPort &getDataPort() { return dcachePort; }
243
244 /** Return a reference to the instruction port. */
245 virtual CpuPort &getInstPort() { return icachePort; }
246
247 public:
248
249 virtual void serialize(std::ostream &os);
250 virtual void unserialize(Checkpoint *cp, const std::string §ion);
251
252 virtual unsigned int drain(Event *drain_event);
253 virtual void resume();
254
255 void switchOut();
256 void takeOverFrom(BaseCPU *oldCPU);
257
258 virtual void activateContext(ThreadID thread_num, Cycles delay);
259 virtual void suspendContext(ThreadID thread_num);
260
261 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
262
263 Fault writeMem(uint8_t *data, unsigned size,
264 Addr addr, unsigned flags, uint64_t *res);
265
266 void fetch();
267 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
268 void completeIfetch(PacketPtr );
269 void completeDataAccess(PacketPtr pkt);
270 void advanceInst(Fault fault);
271
|