timing.hh (8229:78bf55f23338) timing.hh (8443:530ff1bc8d70)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35#include "cpu/translation.hh"
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
47 public:
48 Event *drainEvent;
49
50 private:
51
52 /*
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for
58 * a retry, it's pointer is NULL. After each fragment has successfully
59 * been processed, the "outstanding" counter is decremented. Once the
60 * count is zero, the entire larger access is complete.
61 */
62 class SplitMainSenderState : public Packet::SenderState
63 {
64 public:
65 int outstanding;
66 PacketPtr fragments[2];
67
68 int
69 getPendingFragment()
70 {
71 if (fragments[0]) {
72 return 0;
73 } else if (fragments[1]) {
74 return 1;
75 } else {
76 return -1;
77 }
78 }
79 };
80
81 class SplitFragmentSenderState : public Packet::SenderState
82 {
83 public:
84 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85 bigPkt(_bigPkt), index(_index)
86 {}
87 PacketPtr bigPkt;
88 int index;
89
90 void
91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
99 class FetchTranslation : public BaseTLB::Translation
100 {
101 protected:
102 TimingSimpleCPU *cpu;
103
104 public:
105 FetchTranslation(TimingSimpleCPU *_cpu)
106 : cpu(_cpu)
107 {}
108
109 void
110 markDelayed()
111 {
112 assert(cpu->_status == Running);
113 cpu->_status = ITBWaitResponse;
114 }
115
116 void
117 finish(Fault fault, RequestPtr req, ThreadContext *tc,
118 BaseTLB::Mode mode)
119 {
120 cpu->sendFetch(fault, req, tc);
121 }
122 };
123 FetchTranslation fetchTranslation;
124
125 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
126 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
127 uint8_t *data, bool read);
128
129 void translationFault(Fault fault);
130
131 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
140 class CpuPort : public Port
141 {
142 protected:
143 TimingSimpleCPU *cpu;
144 Tick lat;
145
146 public:
147
148 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
149 : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
150 { }
151
152 bool snoopRangeSent;
153
154 protected:
155
156 virtual Tick recvAtomic(PacketPtr pkt);
157
158 virtual void recvFunctional(PacketPtr pkt);
159
160 virtual void recvStatusChange(Status status);
161
162 virtual void getDeviceAddressRanges(AddrRangeList &resp,
163 bool &snoop)
164 { resp.clear(); snoop = false; }
165
166 struct TickEvent : public Event
167 {
168 PacketPtr pkt;
169 TimingSimpleCPU *cpu;
170 CpuPort *port;
171
172 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
173 const char *description() const { return "Timing CPU tick"; }
174 void schedule(PacketPtr _pkt, Tick t);
175 };
176
177 EventWrapper<Port, &Port::sendRetry> retryEvent;
178 };
179
180 class IcachePort : public CpuPort
181 {
182 public:
183
184 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
185 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
186 { }
187
188 protected:
189
190 virtual bool recvTiming(PacketPtr pkt);
191
192 virtual void recvRetry();
193
194 struct ITickEvent : public TickEvent
195 {
196
197 ITickEvent(TimingSimpleCPU *_cpu)
198 : TickEvent(_cpu) {}
199 void process();
200 const char *description() const { return "Timing CPU icache tick"; }
201 };
202
203 ITickEvent tickEvent;
204
205 };
206
207 class DcachePort : public CpuPort
208 {
209 public:
210
211 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
212 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
213 { }
214
215 virtual void setPeer(Port *port);
216
217 protected:
218
219 virtual bool recvTiming(PacketPtr pkt);
220
221 virtual void recvRetry();
222
223 struct DTickEvent : public TickEvent
224 {
225 DTickEvent(TimingSimpleCPU *_cpu)
226 : TickEvent(_cpu) {}
227 void process();
228 const char *description() const { return "Timing CPU dcache tick"; }
229 };
230
231 DTickEvent tickEvent;
232
233 };
234
235 IcachePort icachePort;
236 DcachePort dcachePort;
237
238 PacketPtr ifetch_pkt;
239 PacketPtr dcache_pkt;
240
241 Tick previousTick;
242
243 public:
244
245 virtual Port *getPort(const std::string &if_name, int idx = -1);
246
247 virtual void serialize(std::ostream &os);
248 virtual void unserialize(Checkpoint *cp, const std::string &section);
249
250 virtual unsigned int drain(Event *drain_event);
251 virtual void resume();
252
253 void switchOut();
254 void takeOverFrom(BaseCPU *oldCPU);
255
256 virtual void activateContext(int thread_num, int delay);
257 virtual void suspendContext(int thread_num);
258
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35#include "cpu/translation.hh"
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
47 public:
48 Event *drainEvent;
49
50 private:
51
52 /*
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for
58 * a retry, it's pointer is NULL. After each fragment has successfully
59 * been processed, the "outstanding" counter is decremented. Once the
60 * count is zero, the entire larger access is complete.
61 */
62 class SplitMainSenderState : public Packet::SenderState
63 {
64 public:
65 int outstanding;
66 PacketPtr fragments[2];
67
68 int
69 getPendingFragment()
70 {
71 if (fragments[0]) {
72 return 0;
73 } else if (fragments[1]) {
74 return 1;
75 } else {
76 return -1;
77 }
78 }
79 };
80
81 class SplitFragmentSenderState : public Packet::SenderState
82 {
83 public:
84 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85 bigPkt(_bigPkt), index(_index)
86 {}
87 PacketPtr bigPkt;
88 int index;
89
90 void
91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
99 class FetchTranslation : public BaseTLB::Translation
100 {
101 protected:
102 TimingSimpleCPU *cpu;
103
104 public:
105 FetchTranslation(TimingSimpleCPU *_cpu)
106 : cpu(_cpu)
107 {}
108
109 void
110 markDelayed()
111 {
112 assert(cpu->_status == Running);
113 cpu->_status = ITBWaitResponse;
114 }
115
116 void
117 finish(Fault fault, RequestPtr req, ThreadContext *tc,
118 BaseTLB::Mode mode)
119 {
120 cpu->sendFetch(fault, req, tc);
121 }
122 };
123 FetchTranslation fetchTranslation;
124
125 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
126 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
127 uint8_t *data, bool read);
128
129 void translationFault(Fault fault);
130
131 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
140 class CpuPort : public Port
141 {
142 protected:
143 TimingSimpleCPU *cpu;
144 Tick lat;
145
146 public:
147
148 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
149 : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
150 { }
151
152 bool snoopRangeSent;
153
154 protected:
155
156 virtual Tick recvAtomic(PacketPtr pkt);
157
158 virtual void recvFunctional(PacketPtr pkt);
159
160 virtual void recvStatusChange(Status status);
161
162 virtual void getDeviceAddressRanges(AddrRangeList &resp,
163 bool &snoop)
164 { resp.clear(); snoop = false; }
165
166 struct TickEvent : public Event
167 {
168 PacketPtr pkt;
169 TimingSimpleCPU *cpu;
170 CpuPort *port;
171
172 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
173 const char *description() const { return "Timing CPU tick"; }
174 void schedule(PacketPtr _pkt, Tick t);
175 };
176
177 EventWrapper<Port, &Port::sendRetry> retryEvent;
178 };
179
180 class IcachePort : public CpuPort
181 {
182 public:
183
184 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
185 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
186 { }
187
188 protected:
189
190 virtual bool recvTiming(PacketPtr pkt);
191
192 virtual void recvRetry();
193
194 struct ITickEvent : public TickEvent
195 {
196
197 ITickEvent(TimingSimpleCPU *_cpu)
198 : TickEvent(_cpu) {}
199 void process();
200 const char *description() const { return "Timing CPU icache tick"; }
201 };
202
203 ITickEvent tickEvent;
204
205 };
206
207 class DcachePort : public CpuPort
208 {
209 public:
210
211 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
212 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
213 { }
214
215 virtual void setPeer(Port *port);
216
217 protected:
218
219 virtual bool recvTiming(PacketPtr pkt);
220
221 virtual void recvRetry();
222
223 struct DTickEvent : public TickEvent
224 {
225 DTickEvent(TimingSimpleCPU *_cpu)
226 : TickEvent(_cpu) {}
227 void process();
228 const char *description() const { return "Timing CPU dcache tick"; }
229 };
230
231 DTickEvent tickEvent;
232
233 };
234
235 IcachePort icachePort;
236 DcachePort dcachePort;
237
238 PacketPtr ifetch_pkt;
239 PacketPtr dcache_pkt;
240
241 Tick previousTick;
242
243 public:
244
245 virtual Port *getPort(const std::string &if_name, int idx = -1);
246
247 virtual void serialize(std::ostream &os);
248 virtual void unserialize(Checkpoint *cp, const std::string &section);
249
250 virtual unsigned int drain(Event *drain_event);
251 virtual void resume();
252
253 void switchOut();
254 void takeOverFrom(BaseCPU *oldCPU);
255
256 virtual void activateContext(int thread_num, int delay);
257 virtual void suspendContext(int thread_num);
258
259 template <class T>
260 Fault read(Addr addr, T &data, unsigned flags);
261
262 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
263
259 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
260
264 template <class T>
265 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
266
267 Fault writeBytes(uint8_t *data, unsigned size,
268 Addr addr, unsigned flags, uint64_t *res);
269
270 void fetch();
271 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
272 void completeIfetch(PacketPtr );
273 void completeDataAccess(PacketPtr pkt);
274 void advanceInst(Fault fault);
275
276 /**
277 * Print state of address in memory system via PrintReq (for
278 * debugging).
279 */
280 void printAddr(Addr a);
281
282 /**
283 * Finish a DTB translation.
284 * @param state The DTB translation state.
285 */
286 void finishTranslation(WholeTranslationState *state);
287
288 private:
289
261 Fault writeBytes(uint8_t *data, unsigned size,
262 Addr addr, unsigned flags, uint64_t *res);
263
264 void fetch();
265 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
266 void completeIfetch(PacketPtr );
267 void completeDataAccess(PacketPtr pkt);
268 void advanceInst(Fault fault);
269
270 /**
271 * Print state of address in memory system via PrintReq (for
272 * debugging).
273 */
274 void printAddr(Addr a);
275
276 /**
277 * Finish a DTB translation.
278 * @param state The DTB translation state.
279 */
280 void finishTranslation(WholeTranslationState *state);
281
282 private:
283
290 // The backend for writeBytes and write. It's the same as writeBytes, but
291 // doesn't make a copy of data.
292 Fault writeTheseBytes(uint8_t *data, unsigned size,
293 Addr addr, unsigned flags, uint64_t *res);
294
295 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
296 FetchEvent fetchEvent;
297
298 struct IprEvent : Event {
299 Packet *pkt;
300 TimingSimpleCPU *cpu;
301 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
302 virtual void process();
303 virtual const char *description() const;
304 };
305
306 void completeDrain();
307};
308
309#endif // __CPU_SIMPLE_TIMING_HH__
284 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
285 FetchEvent fetchEvent;
286
287 struct IprEvent : Event {
288 Packet *pkt;
289 TimingSimpleCPU *cpu;
290 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
291 virtual void process();
292 virtual const char *description() const;
293 };
294
295 void completeDrain();
296};
297
298#endif // __CPU_SIMPLE_TIMING_HH__