timing.hh (5336:c7e21f4e5a2e) | timing.hh (5496:6899b894166f) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_SIMPLE_TIMING_HH__ 32#define __CPU_SIMPLE_TIMING_HH__ 33 34#include "cpu/simple/base.hh" 35 36class TimingSimpleCPU : public BaseSimpleCPU 37{ 38 public: 39 40 struct Params : public BaseSimpleCPU::Params { 41 }; 42 43 TimingSimpleCPU(Params *params); 44 virtual ~TimingSimpleCPU(); 45 46 virtual void init(); 47 48 public: | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_SIMPLE_TIMING_HH__ 32#define __CPU_SIMPLE_TIMING_HH__ 33 34#include "cpu/simple/base.hh" 35 36class TimingSimpleCPU : public BaseSimpleCPU 37{ 38 public: 39 40 struct Params : public BaseSimpleCPU::Params { 41 }; 42 43 TimingSimpleCPU(Params *params); 44 virtual ~TimingSimpleCPU(); 45 46 virtual void init(); 47 48 public: |
49 // 50 enum Status { 51 Idle, 52 Running, 53 IcacheRetry, 54 IcacheWaitResponse, 55 IcacheWaitSwitch, 56 DcacheRetry, 57 DcacheWaitResponse, 58 DcacheWaitSwitch, 59 SwitchedOut 60 }; 61 62 protected: 63 Status _status; 64 65 Status status() const { return _status; } 66 | |
67 Event *drainEvent; 68 69 private: 70 71 class CpuPort : public Port 72 { 73 protected: 74 TimingSimpleCPU *cpu; 75 Tick lat; 76 77 public: 78 79 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 80 : Port(_name, _cpu), cpu(_cpu), lat(_lat) 81 { } 82 83 bool snoopRangeSent; 84 85 protected: 86 87 virtual Tick recvAtomic(PacketPtr pkt); 88 89 virtual void recvFunctional(PacketPtr pkt); 90 91 virtual void recvStatusChange(Status status); 92 93 virtual void getDeviceAddressRanges(AddrRangeList &resp, 94 bool &snoop) 95 { resp.clear(); snoop = false; } 96 97 struct TickEvent : public Event 98 { 99 PacketPtr pkt; 100 TimingSimpleCPU *cpu; 101 102 TickEvent(TimingSimpleCPU *_cpu) 103 :Event(&mainEventQueue), cpu(_cpu) {} 104 const char *description() const { return "Timing CPU tick"; } 105 void schedule(PacketPtr _pkt, Tick t); 106 }; 107 108 }; 109 110 class IcachePort : public CpuPort 111 { 112 public: 113 114 IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 115 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 116 { } 117 118 protected: 119 120 virtual bool recvTiming(PacketPtr pkt); 121 122 virtual void recvRetry(); 123 124 struct ITickEvent : public TickEvent 125 { 126 127 ITickEvent(TimingSimpleCPU *_cpu) 128 : TickEvent(_cpu) {} 129 void process(); 130 const char *description() const { return "Timing CPU icache tick"; } 131 }; 132 133 ITickEvent tickEvent; 134 135 }; 136 137 class DcachePort : public CpuPort 138 { 139 public: 140 141 DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 142 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 143 { } 144 145 virtual void setPeer(Port *port); 146 147 protected: 148 149 virtual bool recvTiming(PacketPtr pkt); 150 151 virtual void recvRetry(); 152 153 struct DTickEvent : public TickEvent 154 { 155 DTickEvent(TimingSimpleCPU *_cpu) 156 : TickEvent(_cpu) {} 157 void process(); 158 const char *description() const { return "Timing CPU dcache tick"; } 159 }; 160 161 DTickEvent tickEvent; 162 163 }; 164 165 IcachePort icachePort; 166 DcachePort dcachePort; 167 168 PacketPtr ifetch_pkt; 169 PacketPtr dcache_pkt; 170 171 Tick previousTick; 172 173 public: 174 175 virtual Port *getPort(const std::string &if_name, int idx = -1); 176 177 virtual void serialize(std::ostream &os); 178 virtual void unserialize(Checkpoint *cp, const std::string §ion); 179 180 virtual unsigned int drain(Event *drain_event); 181 virtual void resume(); 182 183 void switchOut(); 184 void takeOverFrom(BaseCPU *oldCPU); 185 186 virtual void activateContext(int thread_num, int delay); 187 virtual void suspendContext(int thread_num); 188 189 template <class T> 190 Fault read(Addr addr, T &data, unsigned flags); 191 192 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 193 int size, unsigned flags); 194 195 template <class T> 196 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 197 198 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 199 int size, unsigned flags); 200 201 void fetch(); 202 void completeIfetch(PacketPtr ); 203 void completeDataAccess(PacketPtr ); 204 void advanceInst(Fault fault); 205 206 /** 207 * Print state of address in memory system via PrintReq (for 208 * debugging). 209 */ 210 void printAddr(Addr a); 211 212 private: 213 214 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 215 FetchEvent *fetchEvent; 216 217 struct IprEvent : Event { 218 Packet *pkt; 219 TimingSimpleCPU *cpu; 220 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 221 virtual void process(); 222 virtual const char *description() const; 223 }; 224 225 void completeDrain(); 226}; 227 228#endif // __CPU_SIMPLE_TIMING_HH__ | 49 Event *drainEvent; 50 51 private: 52 53 class CpuPort : public Port 54 { 55 protected: 56 TimingSimpleCPU *cpu; 57 Tick lat; 58 59 public: 60 61 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 62 : Port(_name, _cpu), cpu(_cpu), lat(_lat) 63 { } 64 65 bool snoopRangeSent; 66 67 protected: 68 69 virtual Tick recvAtomic(PacketPtr pkt); 70 71 virtual void recvFunctional(PacketPtr pkt); 72 73 virtual void recvStatusChange(Status status); 74 75 virtual void getDeviceAddressRanges(AddrRangeList &resp, 76 bool &snoop) 77 { resp.clear(); snoop = false; } 78 79 struct TickEvent : public Event 80 { 81 PacketPtr pkt; 82 TimingSimpleCPU *cpu; 83 84 TickEvent(TimingSimpleCPU *_cpu) 85 :Event(&mainEventQueue), cpu(_cpu) {} 86 const char *description() const { return "Timing CPU tick"; } 87 void schedule(PacketPtr _pkt, Tick t); 88 }; 89 90 }; 91 92 class IcachePort : public CpuPort 93 { 94 public: 95 96 IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 97 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 98 { } 99 100 protected: 101 102 virtual bool recvTiming(PacketPtr pkt); 103 104 virtual void recvRetry(); 105 106 struct ITickEvent : public TickEvent 107 { 108 109 ITickEvent(TimingSimpleCPU *_cpu) 110 : TickEvent(_cpu) {} 111 void process(); 112 const char *description() const { return "Timing CPU icache tick"; } 113 }; 114 115 ITickEvent tickEvent; 116 117 }; 118 119 class DcachePort : public CpuPort 120 { 121 public: 122 123 DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 124 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 125 { } 126 127 virtual void setPeer(Port *port); 128 129 protected: 130 131 virtual bool recvTiming(PacketPtr pkt); 132 133 virtual void recvRetry(); 134 135 struct DTickEvent : public TickEvent 136 { 137 DTickEvent(TimingSimpleCPU *_cpu) 138 : TickEvent(_cpu) {} 139 void process(); 140 const char *description() const { return "Timing CPU dcache tick"; } 141 }; 142 143 DTickEvent tickEvent; 144 145 }; 146 147 IcachePort icachePort; 148 DcachePort dcachePort; 149 150 PacketPtr ifetch_pkt; 151 PacketPtr dcache_pkt; 152 153 Tick previousTick; 154 155 public: 156 157 virtual Port *getPort(const std::string &if_name, int idx = -1); 158 159 virtual void serialize(std::ostream &os); 160 virtual void unserialize(Checkpoint *cp, const std::string §ion); 161 162 virtual unsigned int drain(Event *drain_event); 163 virtual void resume(); 164 165 void switchOut(); 166 void takeOverFrom(BaseCPU *oldCPU); 167 168 virtual void activateContext(int thread_num, int delay); 169 virtual void suspendContext(int thread_num); 170 171 template <class T> 172 Fault read(Addr addr, T &data, unsigned flags); 173 174 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 175 int size, unsigned flags); 176 177 template <class T> 178 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 179 180 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 181 int size, unsigned flags); 182 183 void fetch(); 184 void completeIfetch(PacketPtr ); 185 void completeDataAccess(PacketPtr ); 186 void advanceInst(Fault fault); 187 188 /** 189 * Print state of address in memory system via PrintReq (for 190 * debugging). 191 */ 192 void printAddr(Addr a); 193 194 private: 195 196 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 197 FetchEvent *fetchEvent; 198 199 struct IprEvent : Event { 200 Packet *pkt; 201 TimingSimpleCPU *cpu; 202 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 203 virtual void process(); 204 virtual const char *description() const; 205 }; 206 207 void completeDrain(); 208}; 209 210#endif // __CPU_SIMPLE_TIMING_HH__ |