timing.hh (2644:8a45565c2c04) timing.hh (2657:b119b774656b)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_SIMPLE_TIMING_HH__
30#define __CPU_SIMPLE_TIMING_HH__
31
32#include "cpu/simple/base.hh"
33
34class TimingSimpleCPU : public BaseSimpleCPU
35{
36 public:
37
38 struct Params : public BaseSimpleCPU::Params {
39 };
40
41 TimingSimpleCPU(Params *params);
42 virtual ~TimingSimpleCPU();
43
44 virtual void init();
45
46 public:
47 //
48 enum Status {
49 Idle,
50 Running,
51 IcacheRetry,
52 IcacheWaitResponse,
53 IcacheWaitSwitch,
54 DcacheRetry,
55 DcacheWaitResponse,
56 DcacheWaitSwitch,
57 SwitchedOut
58 };
59
60 protected:
61 Status _status;
62
63 Status status() const { return _status; }
64
65 private:
66
67 class CpuPort : public Port
68 {
69 protected:
70 TimingSimpleCPU *cpu;
71
72 public:
73
74 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
75 : Port(_name), cpu(_cpu)
76 { }
77
78 protected:
79
80 virtual Tick recvAtomic(Packet *pkt);
81
82 virtual void recvFunctional(Packet *pkt);
83
84 virtual void recvStatusChange(Status status);
85
86 virtual void getDeviceAddressRanges(AddrRangeList &resp,
87 AddrRangeList &snoop)
88 { resp.clear(); snoop.clear(); }
89 };
90
91 class IcachePort : public CpuPort
92 {
93 public:
94
95 IcachePort(TimingSimpleCPU *_cpu)
96 : CpuPort(_cpu->name() + "-iport", _cpu)
97 { }
98
99 protected:
100
101 virtual bool recvTiming(Packet *pkt);
102
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_SIMPLE_TIMING_HH__
30#define __CPU_SIMPLE_TIMING_HH__
31
32#include "cpu/simple/base.hh"
33
34class TimingSimpleCPU : public BaseSimpleCPU
35{
36 public:
37
38 struct Params : public BaseSimpleCPU::Params {
39 };
40
41 TimingSimpleCPU(Params *params);
42 virtual ~TimingSimpleCPU();
43
44 virtual void init();
45
46 public:
47 //
48 enum Status {
49 Idle,
50 Running,
51 IcacheRetry,
52 IcacheWaitResponse,
53 IcacheWaitSwitch,
54 DcacheRetry,
55 DcacheWaitResponse,
56 DcacheWaitSwitch,
57 SwitchedOut
58 };
59
60 protected:
61 Status _status;
62
63 Status status() const { return _status; }
64
65 private:
66
67 class CpuPort : public Port
68 {
69 protected:
70 TimingSimpleCPU *cpu;
71
72 public:
73
74 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
75 : Port(_name), cpu(_cpu)
76 { }
77
78 protected:
79
80 virtual Tick recvAtomic(Packet *pkt);
81
82 virtual void recvFunctional(Packet *pkt);
83
84 virtual void recvStatusChange(Status status);
85
86 virtual void getDeviceAddressRanges(AddrRangeList &resp,
87 AddrRangeList &snoop)
88 { resp.clear(); snoop.clear(); }
89 };
90
91 class IcachePort : public CpuPort
92 {
93 public:
94
95 IcachePort(TimingSimpleCPU *_cpu)
96 : CpuPort(_cpu->name() + "-iport", _cpu)
97 { }
98
99 protected:
100
101 virtual bool recvTiming(Packet *pkt);
102
103 virtual Packet *recvRetry();
103 virtual void recvRetry();
104 };
105
106 class DcachePort : public CpuPort
107 {
108 public:
109
110 DcachePort(TimingSimpleCPU *_cpu)
111 : CpuPort(_cpu->name() + "-dport", _cpu)
112 { }
113
114 protected:
115
116 virtual bool recvTiming(Packet *pkt);
117
104 };
105
106 class DcachePort : public CpuPort
107 {
108 public:
109
110 DcachePort(TimingSimpleCPU *_cpu)
111 : CpuPort(_cpu->name() + "-dport", _cpu)
112 { }
113
114 protected:
115
116 virtual bool recvTiming(Packet *pkt);
117
118 virtual Packet *recvRetry();
118 virtual void recvRetry();
119 };
120
121 IcachePort icachePort;
122 DcachePort dcachePort;
123
124 Packet *ifetch_pkt;
125 Packet *dcache_pkt;
126
127 public:
128
129 virtual void serialize(std::ostream &os);
130 virtual void unserialize(Checkpoint *cp, const std::string &section);
131
132 void switchOut(Sampler *s);
133 void takeOverFrom(BaseCPU *oldCPU);
134
135 virtual void activateContext(int thread_num, int delay);
136 virtual void suspendContext(int thread_num);
137
138 template <class T>
139 Fault read(Addr addr, T &data, unsigned flags);
140
141 template <class T>
142 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
143
144 void fetch();
145 void completeIfetch(Packet *);
146 void completeDataAccess(Packet *);
147 void advanceInst(Fault fault);
148};
149
150#endif // __CPU_SIMPLE_TIMING_HH__
119 };
120
121 IcachePort icachePort;
122 DcachePort dcachePort;
123
124 Packet *ifetch_pkt;
125 Packet *dcache_pkt;
126
127 public:
128
129 virtual void serialize(std::ostream &os);
130 virtual void unserialize(Checkpoint *cp, const std::string &section);
131
132 void switchOut(Sampler *s);
133 void takeOverFrom(BaseCPU *oldCPU);
134
135 virtual void activateContext(int thread_num, int delay);
136 virtual void suspendContext(int thread_num);
137
138 template <class T>
139 Fault read(Addr addr, T &data, unsigned flags);
140
141 template <class T>
142 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
143
144 void fetch();
145 void completeIfetch(Packet *);
146 void completeDataAccess(Packet *);
147 void advanceInst(Fault fault);
148};
149
150#endif // __CPU_SIMPLE_TIMING_HH__