3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_TIMING_HH__
44#define __CPU_SIMPLE_TIMING_HH__
45
46#include "cpu/simple/base.hh"
47#include "cpu/simple/exec_context.hh"
48#include "cpu/translation.hh"
49#include "params/TimingSimpleCPU.hh"
50
51class TimingSimpleCPU : public BaseSimpleCPU
52{
53 public:
54
55 TimingSimpleCPU(TimingSimpleCPUParams * params);
56 virtual ~TimingSimpleCPU();
57
58 void init() override;
59
60 private:
61
62 /*
63 * If an access needs to be broken into fragments, currently at most two,
64 * the the following two classes are used as the sender state of the
65 * packets so the CPU can keep track of everything. In the main packet
66 * sender state, there's an array with a spot for each fragment. If a
67 * fragment has already been accepted by the CPU, aka isn't waiting for
68 * a retry, it's pointer is NULL. After each fragment has successfully
69 * been processed, the "outstanding" counter is decremented. Once the
70 * count is zero, the entire larger access is complete.
71 */
72 class SplitMainSenderState : public Packet::SenderState
73 {
74 public:
75 int outstanding;
76 PacketPtr fragments[2];
77
78 int
79 getPendingFragment()
80 {
81 if (fragments[0]) {
82 return 0;
83 } else if (fragments[1]) {
84 return 1;
85 } else {
86 return -1;
87 }
88 }
89 };
90
91 class SplitFragmentSenderState : public Packet::SenderState
92 {
93 public:
94 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
95 bigPkt(_bigPkt), index(_index)
96 {}
97 PacketPtr bigPkt;
98 int index;
99
100 void
101 clearFromParent()
102 {
103 SplitMainSenderState * main_send_state =
104 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
105 main_send_state->fragments[index] = NULL;
106 }
107 };
108
109 class FetchTranslation : public BaseTLB::Translation
110 {
111 protected:
112 TimingSimpleCPU *cpu;
113
114 public:
115 FetchTranslation(TimingSimpleCPU *_cpu)
116 : cpu(_cpu)
117 {}
118
119 void
120 markDelayed()
121 {
122 assert(cpu->_status == BaseSimpleCPU::Running);
123 cpu->_status = ITBWaitResponse;
124 }
125
126 void
127 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
128 BaseTLB::Mode mode)
129 {
130 cpu->sendFetch(fault, req, tc);
131 }
132 };
133 FetchTranslation fetchTranslation;
134
135 void threadSnoop(PacketPtr pkt, ThreadID sender);
136 void sendData(const RequestPtr &req,
137 uint8_t *data, uint64_t *res, bool read);
138 void sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
139 const RequestPtr &req,
140 uint8_t *data, bool read);
141
142 void translationFault(const Fault &fault);
143
144 PacketPtr buildPacket(const RequestPtr &req, bool read);
145 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
146 const RequestPtr &req1, const RequestPtr &req2,
147 const RequestPtr &req,
148 uint8_t *data, bool read);
149
150 bool handleReadPacket(PacketPtr pkt);
151 // This function always implicitly uses dcache_pkt.
152 bool handleWritePacket();
153
154 /**
155 * A TimingCPUPort overrides the default behaviour of the
156 * recvTiming and recvRetry and implements events for the
157 * scheduling of handling of incoming packets in the following
158 * cycle.
159 */
160 class TimingCPUPort : public MasterPort
161 {
162 public:
163
164 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
165 : MasterPort(_name, _cpu), cpu(_cpu),
166 retryRespEvent([this]{ sendRetryResp(); }, name())
167 { }
168
169 protected:
170
171 TimingSimpleCPU* cpu;
172
173 struct TickEvent : public Event
174 {
175 PacketPtr pkt;
176 TimingSimpleCPU *cpu;
177
178 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
179 const char *description() const { return "Timing CPU tick"; }
180 void schedule(PacketPtr _pkt, Tick t);
181 };
182
183 EventFunctionWrapper retryRespEvent;
184 };
185
186 class IcachePort : public TimingCPUPort
187 {
188 public:
189
190 IcachePort(TimingSimpleCPU *_cpu)
191 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
192 tickEvent(_cpu)
193 { }
194
195 protected:
196
197 virtual bool recvTimingResp(PacketPtr pkt);
198
199 virtual void recvReqRetry();
200
201 struct ITickEvent : public TickEvent
202 {
203
204 ITickEvent(TimingSimpleCPU *_cpu)
205 : TickEvent(_cpu) {}
206 void process();
207 const char *description() const { return "Timing CPU icache tick"; }
208 };
209
210 ITickEvent tickEvent;
211
212 };
213
214 class DcachePort : public TimingCPUPort
215 {
216 public:
217
218 DcachePort(TimingSimpleCPU *_cpu)
219 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
220 tickEvent(_cpu)
221 {
222 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
223 }
224
225 Addr cacheBlockMask;
226 protected:
227
228 /** Snoop a coherence request, we need to check if this causes
229 * a wakeup event on a cpu that is monitoring an address
230 */
231 virtual void recvTimingSnoopReq(PacketPtr pkt);
232 virtual void recvFunctionalSnoop(PacketPtr pkt);
233
234 virtual bool recvTimingResp(PacketPtr pkt);
235
236 virtual void recvReqRetry();
237
238 virtual bool isSnooping() const {
239 return true;
240 }
241
242 struct DTickEvent : public TickEvent
243 {
244 DTickEvent(TimingSimpleCPU *_cpu)
245 : TickEvent(_cpu) {}
246 void process();
247 const char *description() const { return "Timing CPU dcache tick"; }
248 };
249
250 DTickEvent tickEvent;
251
252 };
253
254 void updateCycleCounts();
255
256 IcachePort icachePort;
257 DcachePort dcachePort;
258
259 PacketPtr ifetch_pkt;
260 PacketPtr dcache_pkt;
261
262 Cycles previousCycle;
263
264 protected:
265
266 /** Return a reference to the data port. */
267 MasterPort &getDataPort() override { return dcachePort; }
268
269 /** Return a reference to the instruction port. */
270 MasterPort &getInstPort() override { return icachePort; }
271
272 public:
273
274 DrainState drain() override;
275 void drainResume() override;
276
277 void switchOut() override;
278 void takeOverFrom(BaseCPU *oldCPU) override;
279
280 void verifyMemoryMode() const override;
281
282 void activateContext(ThreadID thread_num) override;
283 void suspendContext(ThreadID thread_num) override;
284
285 Fault initiateMemRead(Addr addr, unsigned size,
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_TIMING_HH__
44#define __CPU_SIMPLE_TIMING_HH__
45
46#include "cpu/simple/base.hh"
47#include "cpu/simple/exec_context.hh"
48#include "cpu/translation.hh"
49#include "params/TimingSimpleCPU.hh"
50
51class TimingSimpleCPU : public BaseSimpleCPU
52{
53 public:
54
55 TimingSimpleCPU(TimingSimpleCPUParams * params);
56 virtual ~TimingSimpleCPU();
57
58 void init() override;
59
60 private:
61
62 /*
63 * If an access needs to be broken into fragments, currently at most two,
64 * the the following two classes are used as the sender state of the
65 * packets so the CPU can keep track of everything. In the main packet
66 * sender state, there's an array with a spot for each fragment. If a
67 * fragment has already been accepted by the CPU, aka isn't waiting for
68 * a retry, it's pointer is NULL. After each fragment has successfully
69 * been processed, the "outstanding" counter is decremented. Once the
70 * count is zero, the entire larger access is complete.
71 */
72 class SplitMainSenderState : public Packet::SenderState
73 {
74 public:
75 int outstanding;
76 PacketPtr fragments[2];
77
78 int
79 getPendingFragment()
80 {
81 if (fragments[0]) {
82 return 0;
83 } else if (fragments[1]) {
84 return 1;
85 } else {
86 return -1;
87 }
88 }
89 };
90
91 class SplitFragmentSenderState : public Packet::SenderState
92 {
93 public:
94 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
95 bigPkt(_bigPkt), index(_index)
96 {}
97 PacketPtr bigPkt;
98 int index;
99
100 void
101 clearFromParent()
102 {
103 SplitMainSenderState * main_send_state =
104 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
105 main_send_state->fragments[index] = NULL;
106 }
107 };
108
109 class FetchTranslation : public BaseTLB::Translation
110 {
111 protected:
112 TimingSimpleCPU *cpu;
113
114 public:
115 FetchTranslation(TimingSimpleCPU *_cpu)
116 : cpu(_cpu)
117 {}
118
119 void
120 markDelayed()
121 {
122 assert(cpu->_status == BaseSimpleCPU::Running);
123 cpu->_status = ITBWaitResponse;
124 }
125
126 void
127 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
128 BaseTLB::Mode mode)
129 {
130 cpu->sendFetch(fault, req, tc);
131 }
132 };
133 FetchTranslation fetchTranslation;
134
135 void threadSnoop(PacketPtr pkt, ThreadID sender);
136 void sendData(const RequestPtr &req,
137 uint8_t *data, uint64_t *res, bool read);
138 void sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
139 const RequestPtr &req,
140 uint8_t *data, bool read);
141
142 void translationFault(const Fault &fault);
143
144 PacketPtr buildPacket(const RequestPtr &req, bool read);
145 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
146 const RequestPtr &req1, const RequestPtr &req2,
147 const RequestPtr &req,
148 uint8_t *data, bool read);
149
150 bool handleReadPacket(PacketPtr pkt);
151 // This function always implicitly uses dcache_pkt.
152 bool handleWritePacket();
153
154 /**
155 * A TimingCPUPort overrides the default behaviour of the
156 * recvTiming and recvRetry and implements events for the
157 * scheduling of handling of incoming packets in the following
158 * cycle.
159 */
160 class TimingCPUPort : public MasterPort
161 {
162 public:
163
164 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
165 : MasterPort(_name, _cpu), cpu(_cpu),
166 retryRespEvent([this]{ sendRetryResp(); }, name())
167 { }
168
169 protected:
170
171 TimingSimpleCPU* cpu;
172
173 struct TickEvent : public Event
174 {
175 PacketPtr pkt;
176 TimingSimpleCPU *cpu;
177
178 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
179 const char *description() const { return "Timing CPU tick"; }
180 void schedule(PacketPtr _pkt, Tick t);
181 };
182
183 EventFunctionWrapper retryRespEvent;
184 };
185
186 class IcachePort : public TimingCPUPort
187 {
188 public:
189
190 IcachePort(TimingSimpleCPU *_cpu)
191 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
192 tickEvent(_cpu)
193 { }
194
195 protected:
196
197 virtual bool recvTimingResp(PacketPtr pkt);
198
199 virtual void recvReqRetry();
200
201 struct ITickEvent : public TickEvent
202 {
203
204 ITickEvent(TimingSimpleCPU *_cpu)
205 : TickEvent(_cpu) {}
206 void process();
207 const char *description() const { return "Timing CPU icache tick"; }
208 };
209
210 ITickEvent tickEvent;
211
212 };
213
214 class DcachePort : public TimingCPUPort
215 {
216 public:
217
218 DcachePort(TimingSimpleCPU *_cpu)
219 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
220 tickEvent(_cpu)
221 {
222 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
223 }
224
225 Addr cacheBlockMask;
226 protected:
227
228 /** Snoop a coherence request, we need to check if this causes
229 * a wakeup event on a cpu that is monitoring an address
230 */
231 virtual void recvTimingSnoopReq(PacketPtr pkt);
232 virtual void recvFunctionalSnoop(PacketPtr pkt);
233
234 virtual bool recvTimingResp(PacketPtr pkt);
235
236 virtual void recvReqRetry();
237
238 virtual bool isSnooping() const {
239 return true;
240 }
241
242 struct DTickEvent : public TickEvent
243 {
244 DTickEvent(TimingSimpleCPU *_cpu)
245 : TickEvent(_cpu) {}
246 void process();
247 const char *description() const { return "Timing CPU dcache tick"; }
248 };
249
250 DTickEvent tickEvent;
251
252 };
253
254 void updateCycleCounts();
255
256 IcachePort icachePort;
257 DcachePort dcachePort;
258
259 PacketPtr ifetch_pkt;
260 PacketPtr dcache_pkt;
261
262 Cycles previousCycle;
263
264 protected:
265
266 /** Return a reference to the data port. */
267 MasterPort &getDataPort() override { return dcachePort; }
268
269 /** Return a reference to the instruction port. */
270 MasterPort &getInstPort() override { return icachePort; }
271
272 public:
273
274 DrainState drain() override;
275 void drainResume() override;
276
277 void switchOut() override;
278 void takeOverFrom(BaseCPU *oldCPU) override;
279
280 void verifyMemoryMode() const override;
281
282 void activateContext(ThreadID thread_num) override;
283 void suspendContext(ThreadID thread_num) override;
284
285 Fault initiateMemRead(Addr addr, unsigned size,
|
290
291 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
292 AtomicOpFunctor *amo_op) override;
293
294 void fetch();
295 void sendFetch(const Fault &fault,
296 const RequestPtr &req, ThreadContext *tc);
297 void completeIfetch(PacketPtr );
298 void completeDataAccess(PacketPtr pkt);
299 void advanceInst(const Fault &fault);
300
301 /** This function is used by the page table walker to determine if it could
302 * translate the a pending request or if the underlying request has been
303 * squashed. This always returns false for the simple timing CPU as it never
304 * executes any instructions speculatively.
305 * @ return Is the current instruction squashed?
306 */
307 bool isSquashed() const { return false; }
308
309 /**
310 * Print state of address in memory system via PrintReq (for
311 * debugging).
312 */
313 void printAddr(Addr a);
314
315 /**
316 * Finish a DTB translation.
317 * @param state The DTB translation state.
318 */
319 void finishTranslation(WholeTranslationState *state);
320
321 private:
322
323 EventFunctionWrapper fetchEvent;
324
325 struct IprEvent : Event {
326 Packet *pkt;
327 TimingSimpleCPU *cpu;
328 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
329 virtual void process();
330 virtual const char *description() const;
331 };
332
333 /**
334 * Check if a system is in a drained state.
335 *
336 * We need to drain if:
337 * <ul>
338 * <li>We are in the middle of a microcode sequence as some CPUs
339 * (e.g., HW accelerated CPUs) can't be started in the middle
340 * of a gem5 microcode sequence.
341 *
342 * <li>Stay at PC is true.
343 *
344 * <li>A fetch event is scheduled. Normally this would never be the
345 * case with microPC() == 0, but right after a context is
346 * activated it can happen.
347 * </ul>
348 */
349 bool isDrained() {
350 SimpleExecContext& t_info = *threadInfo[curThread];
351 SimpleThread* thread = t_info.thread;
352
353 return thread->microPC() == 0 && !t_info.stayAtPC &&
354 !fetchEvent.scheduled();
355 }
356
357 /**
358 * Try to complete a drain request.
359 *
360 * @returns true if the CPU is drained, false otherwise.
361 */
362 bool tryCompleteDrain();
363};
364
365#endif // __CPU_SIMPLE_TIMING_HH__
| 294
295 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
296 AtomicOpFunctor *amo_op) override;
297
298 void fetch();
299 void sendFetch(const Fault &fault,
300 const RequestPtr &req, ThreadContext *tc);
301 void completeIfetch(PacketPtr );
302 void completeDataAccess(PacketPtr pkt);
303 void advanceInst(const Fault &fault);
304
305 /** This function is used by the page table walker to determine if it could
306 * translate the a pending request or if the underlying request has been
307 * squashed. This always returns false for the simple timing CPU as it never
308 * executes any instructions speculatively.
309 * @ return Is the current instruction squashed?
310 */
311 bool isSquashed() const { return false; }
312
313 /**
314 * Print state of address in memory system via PrintReq (for
315 * debugging).
316 */
317 void printAddr(Addr a);
318
319 /**
320 * Finish a DTB translation.
321 * @param state The DTB translation state.
322 */
323 void finishTranslation(WholeTranslationState *state);
324
325 private:
326
327 EventFunctionWrapper fetchEvent;
328
329 struct IprEvent : Event {
330 Packet *pkt;
331 TimingSimpleCPU *cpu;
332 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
333 virtual void process();
334 virtual const char *description() const;
335 };
336
337 /**
338 * Check if a system is in a drained state.
339 *
340 * We need to drain if:
341 * <ul>
342 * <li>We are in the middle of a microcode sequence as some CPUs
343 * (e.g., HW accelerated CPUs) can't be started in the middle
344 * of a gem5 microcode sequence.
345 *
346 * <li>Stay at PC is true.
347 *
348 * <li>A fetch event is scheduled. Normally this would never be the
349 * case with microPC() == 0, but right after a context is
350 * activated it can happen.
351 * </ul>
352 */
353 bool isDrained() {
354 SimpleExecContext& t_info = *threadInfo[curThread];
355 SimpleThread* thread = t_info.thread;
356
357 return thread->microPC() == 0 && !t_info.stayAtPC &&
358 !fetchEvent.scheduled();
359 }
360
361 /**
362 * Try to complete a drain request.
363 *
364 * @returns true if the CPU is drained, false otherwise.
365 */
366 bool tryCompleteDrain();
367};
368
369#endif // __CPU_SIMPLE_TIMING_HH__
|