1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
47 public:
48 Event *drainEvent;
49
50 private:
51
52 class CpuPort : public Port
53 {
54 protected:
55 TimingSimpleCPU *cpu;
56 Tick lat;
57
58 public:
59
60 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
61 : Port(_name, _cpu), cpu(_cpu), lat(_lat)
62 { }
63
64 bool snoopRangeSent;
65
66 protected:
67
68 virtual Tick recvAtomic(PacketPtr pkt);
69
70 virtual void recvFunctional(PacketPtr pkt);
71
72 virtual void recvStatusChange(Status status);
73
74 virtual void getDeviceAddressRanges(AddrRangeList &resp,
75 bool &snoop)
76 { resp.clear(); snoop = false; }
77
78 struct TickEvent : public Event
79 {
80 PacketPtr pkt;
81 TimingSimpleCPU *cpu;
82
83 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
84 const char *description() const { return "Timing CPU tick"; }
85 void schedule(PacketPtr _pkt, Tick t);
86 };
87
88 };
89
90 class IcachePort : public CpuPort
91 {
92 public:
93
94 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
95 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
96 { }
97
98 protected:
99
100 virtual bool recvTiming(PacketPtr pkt);
101
102 virtual void recvRetry();
103
104 struct ITickEvent : public TickEvent
105 {
106
107 ITickEvent(TimingSimpleCPU *_cpu)
108 : TickEvent(_cpu) {}
109 void process();
110 const char *description() const { return "Timing CPU icache tick"; }
111 };
112
113 ITickEvent tickEvent;
114
115 };
116
117 class DcachePort : public CpuPort
118 {
119 public:
120
121 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
122 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
123 { }
124
125 virtual void setPeer(Port *port);
126
127 protected:
128
129 virtual bool recvTiming(PacketPtr pkt);
130
131 virtual void recvRetry();
132
133 struct DTickEvent : public TickEvent
134 {
135 DTickEvent(TimingSimpleCPU *_cpu)
136 : TickEvent(_cpu) {}
137 void process();
138 const char *description() const { return "Timing CPU dcache tick"; }
139 };
140
141 DTickEvent tickEvent;
142
143 };
144
145 IcachePort icachePort;
146 DcachePort dcachePort;
147
148 PacketPtr ifetch_pkt;
149 PacketPtr dcache_pkt;
150
151 Tick previousTick;
152
153 public:
154
155 virtual Port *getPort(const std::string &if_name, int idx = -1);
156
157 virtual void serialize(std::ostream &os);
158 virtual void unserialize(Checkpoint *cp, const std::string &section);
159
160 virtual unsigned int drain(Event *drain_event);
161 virtual void resume();
162
163 void switchOut();
164 void takeOverFrom(BaseCPU *oldCPU);
165
166 virtual void activateContext(int thread_num, int delay);
167 virtual void suspendContext(int thread_num);
168
169 template <class T>
170 Fault read(Addr addr, T &data, unsigned flags);
171
172 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
173 int size, unsigned flags);
174
175 template <class T>
176 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
177
178 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
179 int size, unsigned flags);
180
181 void fetch();
182 void completeIfetch(PacketPtr );
183 void completeDataAccess(PacketPtr );
184 void advanceInst(Fault fault);
185
186 /**
187 * Print state of address in memory system via PrintReq (for
188 * debugging).
189 */
190 void printAddr(Addr a);
191
192 private:
193
194 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
195 FetchEvent fetchEvent;
196
197 struct IprEvent : Event {
198 Packet *pkt;
199 TimingSimpleCPU *cpu;
200 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
201 virtual void process();
202 virtual const char *description() const;
203 };
204
205 void completeDrain();
206};
207
208#endif // __CPU_SIMPLE_TIMING_HH__