1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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39{
40 public:
41
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
44
45 virtual void init();
46
47 public:
48 DrainManager *drainManager;
49
50 private:
51
52 /*
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for

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241 /** Return a reference to the data port. */
242 virtual CpuPort &getDataPort() { return dcachePort; }
243
244 /** Return a reference to the instruction port. */
245 virtual CpuPort &getInstPort() { return icachePort; }
246
247 public:
248
249 virtual void serialize(std::ostream &os);
250 virtual void unserialize(Checkpoint *cp, const std::string &section);
251
252 unsigned int drain(DrainManager *drain_manager);
253 void drainResume();
254
255 void switchOut();
256 void takeOverFrom(BaseCPU *oldCPU);
257
258 virtual void activateContext(ThreadID thread_num, Cycles delay);
259 virtual void suspendContext(ThreadID thread_num);

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297 struct IprEvent : Event {
298 Packet *pkt;
299 TimingSimpleCPU *cpu;
300 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
301 virtual void process();
302 virtual const char *description() const;
303 };
304
305 void completeDrain();
306};
307
308#endif // __CPU_SIMPLE_TIMING_HH__