1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
135
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
139
140 class CpuPort : public Port
141 {
142 protected:
143 TimingSimpleCPU *cpu;
144 Tick lat;
145
146 public:
147
148 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
149 : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
150 { }
151
152 bool snoopRangeSent;
153
154 protected:
155
156 virtual Tick recvAtomic(PacketPtr pkt);
157
158 virtual void recvFunctional(PacketPtr pkt);
159
160 virtual void recvStatusChange(Status status);
161
162 virtual void getDeviceAddressRanges(AddrRangeList &resp,
163 bool &snoop)
164 { resp.clear(); snoop = false; }
165
166 struct TickEvent : public Event
167 {
168 PacketPtr pkt;
169 TimingSimpleCPU *cpu;
170 CpuPort *port;
171
172 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
173 const char *description() const { return "Timing CPU tick"; }
174 void schedule(PacketPtr _pkt, Tick t);
175 };
176
177 EventWrapper<Port, &Port::sendRetry> retryEvent;
178 };
179
180 class IcachePort : public CpuPort
181 {
182 public:
183
184 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
185 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
186 { }
187
188 protected:
189
190 virtual bool recvTiming(PacketPtr pkt);
191
192 virtual void recvRetry();
193

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199 void process();
200 const char *description() const { return "Timing CPU icache tick"; }
201 };
202
203 ITickEvent tickEvent;
204
205 };
206
207 class DcachePort : public CpuPort
208 {
209 public:
210
211 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
212 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
213 { }
214
215 protected:
216
217 virtual bool recvTiming(PacketPtr pkt);
218
219 virtual void recvRetry();
220

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