1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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91 clearFromParent()
92 {
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
96 }
97 };
98
99 Fault buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr &req,
100 Addr split_addr, uint8_t *data, bool read);
101 Fault buildPacket(PacketPtr &pkt, RequestPtr &req, bool read);
102
103 bool handleReadPacket(PacketPtr pkt);
104 // This function always implicitly uses dcache_pkt.
105 bool handleWritePacket();
106
107 class CpuPort : public Port
108 {
109 protected:
110 TimingSimpleCPU *cpu;

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223
224 template <class T>
225 Fault read(Addr addr, T &data, unsigned flags);
226
227 template <class T>
228 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
229
230 void fetch();
231 void completeIfetch(PacketPtr );
232 void completeDataAccess(PacketPtr );
233 void advanceInst(Fault fault);
234
235 /**
236 * Print state of address in memory system via PrintReq (for
237 * debugging).
238 */
239 void printAddr(Addr a);
240

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