1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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198 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
199 int size, unsigned flags);
200
201 void fetch();
202 void completeIfetch(PacketPtr );
203 void completeDataAccess(PacketPtr );
204 void advanceInst(Fault fault);
205
206 private:
207
208 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
209 FetchEvent *fetchEvent;
210
211 struct IprEvent : Event {
212 Packet *pkt;
213 TimingSimpleCPU *cpu;
214 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
215 virtual void process();
216 virtual const char *description();
217 };
218
219 void completeDrain();
220};
221
222#endif // __CPU_SIMPLE_TIMING_HH__