1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 60 unchanged lines hidden (view full) ---

69 Event *fetchEvent;
70
71 private:
72
73 class CpuPort : public Port
74 {
75 protected:
76 TimingSimpleCPU *cpu;
77
78 public:
79
80 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
81 : Port(_name), cpu(_cpu)
82 { }
83
84 protected:
85
86 virtual Tick recvAtomic(Packet *pkt);
87
88 virtual void recvFunctional(Packet *pkt);
89
90 virtual void recvStatusChange(Status status);
91
92 virtual void getDeviceAddressRanges(AddrRangeList &resp,
93 AddrRangeList &snoop)
94 { resp.clear(); snoop.clear(); }
95 };
96
97 class IcachePort : public CpuPort
98 {
99 public:
100
101 IcachePort(TimingSimpleCPU *_cpu)
102 : CpuPort(_cpu->name() + "-iport", _cpu)
103 { }
104
105 protected:
106
107 virtual bool recvTiming(Packet *pkt);
108
109 virtual void recvRetry();
110 };
111
112 class DcachePort : public CpuPort
113 {
114 public:
115
116 DcachePort(TimingSimpleCPU *_cpu)
117 : CpuPort(_cpu->name() + "-dport", _cpu)
118 { }
119
120 protected:
121
122 virtual bool recvTiming(Packet *pkt);
123
124 virtual void recvRetry();
125 };
126
127 IcachePort icachePort;
128 DcachePort dcachePort;
129
130 Packet *ifetch_pkt;
131 Packet *dcache_pkt;
132

--- 31 unchanged lines hidden ---