1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 50 unchanged lines hidden (view full) ---

59 SwitchedOut
60 };
61
62 protected:
63 Status _status;
64
65 Status status() const { return _status; }
66
67 private:
68
69 class CpuPort : public Port
70 {
71 protected:
72 TimingSimpleCPU *cpu;
73
74 public:

--- 51 unchanged lines hidden (view full) ---

126 Packet *ifetch_pkt;
127 Packet *dcache_pkt;
128
129 public:
130
131 virtual void serialize(std::ostream &os);
132 virtual void unserialize(Checkpoint *cp, const std::string &section);
133
134 void switchOut(Sampler *s);
135 void takeOverFrom(BaseCPU *oldCPU);
136
137 virtual void activateContext(int thread_num, int delay);
138 virtual void suspendContext(int thread_num);
139
140 template <class T>
141 Fault read(Addr addr, T &data, unsigned flags);
142
143 template <class T>
144 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
145
146 void fetch();
147 void completeIfetch(Packet *);
148 void completeDataAccess(Packet *);
149 void advanceInst(Fault fault);
150};
151
152#endif // __CPU_SIMPLE_TIMING_HH__