1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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198 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
199 int size, unsigned flags);
200
201 void fetch();
202 void completeIfetch(PacketPtr );
203 void completeDataAccess(PacketPtr );
204 void advanceInst(Fault fault);
205
206 /**
207 * Print state of address in memory system via PrintReq (for
208 * debugging).
209 */
210 void printAddr(Addr a);
211
212 private:
213
214 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
215 FetchEvent *fetchEvent;
216
217 struct IprEvent : Event {
218 Packet *pkt;
219 TimingSimpleCPU *cpu;
220 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
221 virtual void process();
222 virtual const char *description();
223 };
224
225 void completeDrain();
226};
227
228#endif // __CPU_SIMPLE_TIMING_HH__