timing.cc (9837:13a21202375d) timing.cc (10020:2f33cb012383)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 632 unchanged lines hidden (view full) ---

641void
642TimingSimpleCPU::completeIfetch(PacketPtr pkt)
643{
644 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
645 pkt->getAddr() : 0);
646
647 // received a response from the icache: execute the received
648 // instruction
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 632 unchanged lines hidden (view full) ---

641void
642TimingSimpleCPU::completeIfetch(PacketPtr pkt)
643{
644 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
645 pkt->getAddr() : 0);
646
647 // received a response from the icache: execute the received
648 // instruction
649
650 assert(!pkt || !pkt->isError());
651 assert(_status == IcacheWaitResponse);
652
653 _status = BaseSimpleCPU::Running;
654
655 numCycles += curCycle() - previousCycle;
656 previousCycle = curCycle();
657
649 assert(!pkt || !pkt->isError());
650 assert(_status == IcacheWaitResponse);
651
652 _status = BaseSimpleCPU::Running;
653
654 numCycles += curCycle() - previousCycle;
655 previousCycle = curCycle();
656
657 if (pkt)
658 pkt->req->setAccessLatency();
659
660
658 preExecute();
659 if (curStaticInst && curStaticInst->isMemRef()) {
660 // load or store: just send to dcache
661 Fault fault = curStaticInst->initiateAcc(this, traceData);
662
663 // If we're not running now the instruction will complete in a dcache
664 // response callback or the instruction faulted and has started an
665 // ifetch

--- 78 unchanged lines hidden (view full) ---

744TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
745{
746 // received a response from the dcache: complete the load or store
747 // instruction
748 assert(!pkt->isError());
749 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
750 pkt->req->getFlags().isSet(Request::NO_ACCESS));
751
661 preExecute();
662 if (curStaticInst && curStaticInst->isMemRef()) {
663 // load or store: just send to dcache
664 Fault fault = curStaticInst->initiateAcc(this, traceData);
665
666 // If we're not running now the instruction will complete in a dcache
667 // response callback or the instruction faulted and has started an
668 // ifetch

--- 78 unchanged lines hidden (view full) ---

747TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
748{
749 // received a response from the dcache: complete the load or store
750 // instruction
751 assert(!pkt->isError());
752 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
753 pkt->req->getFlags().isSet(Request::NO_ACCESS));
754
755 pkt->req->setAccessLatency();
752 numCycles += curCycle() - previousCycle;
753 previousCycle = curCycle();
754
755 if (pkt->senderState) {
756 SplitFragmentSenderState * send_state =
757 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
758 assert(send_state);
759 delete pkt->req;

--- 160 unchanged lines hidden --- 		756 numCycles += curCycle() - previousCycle;
757 previousCycle = curCycle();
758
759 if (pkt->senderState) {
760 SplitFragmentSenderState * send_state =
761 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
762 assert(send_state);
763 delete pkt->req;

--- 160 unchanged lines hidden ---