timing.cc (9648:f10eb34e3e38) timing.cc (9814:7ad2b0186a32)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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399Fault
400TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
401 unsigned size, unsigned flags)
402{
403 Fault fault;
404 const int asid = 0;
405 const ThreadID tid = 0;
406 const Addr pc = thread->instAddr();
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 390 unchanged lines hidden (view full) ---

399Fault
400TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
401 unsigned size, unsigned flags)
402{
403 Fault fault;
404 const int asid = 0;
405 const ThreadID tid = 0;
406 const Addr pc = thread->instAddr();
407 unsigned block_size = dcachePort.peerBlockSize();
407 unsigned block_size = cacheLineSize();
408 BaseTLB::Mode mode = BaseTLB::Read;
409
410 if (traceData) {
411 traceData->setAddr(addr);
412 }
413
414 RequestPtr req = new Request(asid, addr, size,
415 flags, dataMasterId(), pc, _cpuId, tid);

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468 Addr addr, unsigned flags, uint64_t *res)
469{
470 uint8_t *newData = new uint8_t[size];
471 memcpy(newData, data, size);
472
473 const int asid = 0;
474 const ThreadID tid = 0;
475 const Addr pc = thread->instAddr();
408 BaseTLB::Mode mode = BaseTLB::Read;
409
410 if (traceData) {
411 traceData->setAddr(addr);
412 }
413
414 RequestPtr req = new Request(asid, addr, size,
415 flags, dataMasterId(), pc, _cpuId, tid);

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468 Addr addr, unsigned flags, uint64_t *res)
469{
470 uint8_t *newData = new uint8_t[size];
471 memcpy(newData, data, size);
472
473 const int asid = 0;
474 const ThreadID tid = 0;
475 const Addr pc = thread->instAddr();
476 unsigned block_size = dcachePort.peerBlockSize();
476 unsigned block_size = cacheLineSize();
477 BaseTLB::Mode mode = BaseTLB::Write;
478
479 if (traceData) {
480 traceData->setAddr(addr);
481 }
482
483 RequestPtr req = new Request(asid, addr, size,
484 flags, dataMasterId(), pc, _cpuId, tid);

--- 434 unchanged lines hidden --- 		477 BaseTLB::Mode mode = BaseTLB::Write;
478
479 if (traceData) {
480 traceData->setAddr(addr);
481 }
482
483 RequestPtr req = new Request(asid, addr, size,
484 flags, dataMasterId(), pc, _cpuId, tid);

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