timing.cc (9524:d6ffa982a68b) timing.cc (9648:f10eb34e3e38)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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115 } else {
116 drainManager = drain_manager;
117 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
118
119 // The fetch event can become descheduled if a drain didn't
120 // succeed on the first attempt. We need to reschedule it if
121 // the CPU is waiting for a microcode routine to complete.
122 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 106 unchanged lines hidden (view full) ---

115 } else {
116 drainManager = drain_manager;
117 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
118
119 // The fetch event can become descheduled if a drain didn't
120 // succeed on the first attempt. We need to reschedule it if
121 // the CPU is waiting for a microcode routine to complete.
122 if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
123 schedule(fetchEvent, nextCycle());
123 schedule(fetchEvent, clockEdge());
124
125 return 1;
126 }
127}
128
129void
130TimingSimpleCPU::drainResume()
131{

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611TimingSimpleCPU::advanceInst(Fault fault)
612{
613 if (_status == Faulting)
614 return;
615
616 if (fault != NoFault) {
617 advancePC(fault);
618 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
124
125 return 1;
126 }
127}
128
129void
130TimingSimpleCPU::drainResume()
131{

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611TimingSimpleCPU::advanceInst(Fault fault)
612{
613 if (_status == Faulting)
614 return;
615
616 if (fault != NoFault) {
617 advancePC(fault);
618 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
619 reschedule(fetchEvent, nextCycle(), true);
619 reschedule(fetchEvent, clockEdge(), true);
620 _status = Faulting;
621 return;
622 }
623
624
625 if (!stayAtPC)
626 advancePC(fault);
627

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710 cpu->completeIfetch(pkt);
711}
712
713bool
714TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
715{
716 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
717 // delay processing of returned data until next CPU clock edge
620 _status = Faulting;
621 return;
622 }
623
624
625 if (!stayAtPC)
626 advancePC(fault);
627

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710 cpu->completeIfetch(pkt);
711}
712
713bool
714TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
715{
716 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
717 // delay processing of returned data until next CPU clock edge
718 Tick next_tick = cpu->nextCycle();
718 Tick next_tick = cpu->clockEdge();
719
720 if (next_tick == curTick())
721 cpu->completeIfetch(pkt);
722 else
723 tickEvent.schedule(pkt, next_tick);
724
725 return true;
726}

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802
803 advanceInst(fault);
804}
805
806bool
807TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
808{
809 // delay processing of returned data until next CPU clock edge
719
720 if (next_tick == curTick())
721 cpu->completeIfetch(pkt);
722 else
723 tickEvent.schedule(pkt, next_tick);
724
725 return true;
726}

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802
803 advanceInst(fault);
804}
805
806bool
807TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
808{
809 // delay processing of returned data until next CPU clock edge
810 Tick next_tick = cpu->nextCycle();
810 Tick next_tick = cpu->clockEdge();
811
812 if (next_tick == curTick()) {
813 cpu->completeDataAccess(pkt);
814 } else {
815 if (!tickEvent.scheduled()) {
816 tickEvent.schedule(pkt, next_tick);
817 } else {
818 // In the case of a split transaction and a cache that is

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812 if (next_tick == curTick()) {
813 cpu->completeDataAccess(pkt);
814 } else {
815 if (!tickEvent.scheduled()) {
816 tickEvent.schedule(pkt, next_tick);
817 } else {
818 // In the case of a split transaction and a cache that is

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