timing.cc (9342:6fec8f26e56d) timing.cc (9424:d631aac65246)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61using namespace std;
62using namespace TheISA;
63
64void
65TimingSimpleCPU::init()
66{
67 BaseCPU::init();
68
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61using namespace std;
62using namespace TheISA;
63
64void
65TimingSimpleCPU::init()
66{
67 BaseCPU::init();
68
69 if (!params()->defer_registration &&
70 system->getMemoryMode() != Enums::timing) {
71 fatal("The timing CPU requires the memory system to be in "
72 "'timing' mode.\n");
73 }
74
69 // Initialise the ThreadContext's memory proxies
70 tcBase()->initMemProxies(tcBase());
71
72 if (FullSystem && !params()->defer_registration) {
73 for (int i = 0; i < threadContexts.size(); ++i) {
74 ThreadContext *tc = threadContexts[i];
75 // initialize CPU, including PC
76 TheISA::initCPU(tc, _cpuId);

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135 }
136}
137
138void
139TimingSimpleCPU::drainResume()
140{
141 DPRINTF(SimpleCPU, "Resume\n");
142 if (_status != SwitchedOut && _status != Idle) {
75 // Initialise the ThreadContext's memory proxies
76 tcBase()->initMemProxies(tcBase());
77
78 if (FullSystem && !params()->defer_registration) {
79 for (int i = 0; i < threadContexts.size(); ++i) {
80 ThreadContext *tc = threadContexts[i];
81 // initialize CPU, including PC
82 TheISA::initCPU(tc, _cpuId);

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141 }
142}
143
144void
145TimingSimpleCPU::drainResume()
146{
147 DPRINTF(SimpleCPU, "Resume\n");
148 if (_status != SwitchedOut && _status != Idle) {
143 assert(system->getMemoryMode() == Enums::timing);
149 if (system->getMemoryMode() != Enums::timing) {
150 fatal("The timing CPU requires the memory system to be in "
151 "'timing' mode.\n");
152 }
144
145 if (fetchEvent.scheduled())
146 deschedule(fetchEvent);
147
148 schedule(fetchEvent, nextCycle());
149 }
150
151 setDrainState(Drainable::Running);

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154 if (fetchEvent.scheduled())
155 deschedule(fetchEvent);
156
157 schedule(fetchEvent, nextCycle());
158 }
159
160 setDrainState(Drainable::Running);

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