timing.cc (9152:86c0e6ca5e7c) | timing.cc (9165:f9e3dac185ba) |
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1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 705 unchanged lines hidden (view full) --- 714TimingSimpleCPU::IcachePort::ITickEvent::process() 715{ 716 cpu->completeIfetch(pkt); 717} 718 719bool 720TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 721{ | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 705 unchanged lines hidden (view full) --- 714TimingSimpleCPU::IcachePort::ITickEvent::process() 715{ 716 cpu->completeIfetch(pkt); 717} 718 719bool 720TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 721{ |
722 if (!pkt->wasNacked()) { 723 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 724 // delay processing of returned data until next CPU clock edge 725 Tick next_tick = cpu->nextCycle(curTick()); | 722 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 723 // delay processing of returned data until next CPU clock edge 724 Tick next_tick = cpu->nextCycle(); |
726 | 725 |
727 if (next_tick == curTick()) 728 cpu->completeIfetch(pkt); 729 else 730 tickEvent.schedule(pkt, next_tick); | 726 if (next_tick == curTick()) 727 cpu->completeIfetch(pkt); 728 else 729 tickEvent.schedule(pkt, next_tick); |
731 | 730 |
732 return true; 733 } else { 734 assert(cpu->_status == IcacheWaitResponse); 735 pkt->reinitNacked(); 736 if (!sendTimingReq(pkt)) { 737 cpu->_status = IcacheRetry; 738 cpu->ifetch_pkt = pkt; 739 } 740 } 741 | |
742 return true; 743} 744 745void 746TimingSimpleCPU::IcachePort::recvRetry() 747{ 748 // we shouldn't get a retry unless we have a packet that we're 749 // waiting to transmit --- 84 unchanged lines hidden (view full) --- 834 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 835 changeState(SimObject::Drained); 836 drainEvent->process(); 837} 838 839bool 840TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 841{ | 731 return true; 732} 733 734void 735TimingSimpleCPU::IcachePort::recvRetry() 736{ 737 // we shouldn't get a retry unless we have a packet that we're 738 // waiting to transmit --- 84 unchanged lines hidden (view full) --- 823 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 824 changeState(SimObject::Drained); 825 drainEvent->process(); 826} 827 828bool 829TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 830{ |
842 if (!pkt->wasNacked()) { 843 // delay processing of returned data until next CPU clock edge 844 Tick next_tick = cpu->nextCycle(curTick()); | 831 // delay processing of returned data until next CPU clock edge 832 Tick next_tick = cpu->nextCycle(); |
845 | 833 |
846 if (next_tick == curTick()) { 847 cpu->completeDataAccess(pkt); | 834 if (next_tick == curTick()) { 835 cpu->completeDataAccess(pkt); 836 } else { 837 if (!tickEvent.scheduled()) { 838 tickEvent.schedule(pkt, next_tick); |
848 } else { | 839 } else { |
849 if (!tickEvent.scheduled()) { 850 tickEvent.schedule(pkt, next_tick); 851 } else { 852 // In the case of a split transaction and a cache that is 853 // faster than a CPU we could get two responses before 854 // next_tick expires 855 if (!retryEvent.scheduled()) 856 cpu->schedule(retryEvent, next_tick); 857 return false; 858 } | 840 // In the case of a split transaction and a cache that is 841 // faster than a CPU we could get two responses before 842 // next_tick expires 843 if (!retryEvent.scheduled()) 844 cpu->schedule(retryEvent, next_tick); 845 return false; |
859 } | 846 } |
860 861 return true; 862 } else { 863 assert(cpu->_status == DcacheWaitResponse); 864 pkt->reinitNacked(); 865 if (!sendTimingReq(pkt)) { 866 cpu->_status = DcacheRetry; 867 cpu->dcache_pkt = pkt; 868 } | |
869 } 870 871 return true; 872} 873 874void 875TimingSimpleCPU::DcachePort::DTickEvent::process() 876{ --- 86 unchanged lines hidden --- | 847 } 848 849 return true; 850} 851 852void 853TimingSimpleCPU::DcachePort::DTickEvent::process() 854{ --- 86 unchanged lines hidden --- |