timing.cc (9058:cc47e11ccec1) timing.cc (9152:86c0e6ca5e7c)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 34 unchanged lines hidden (view full) ---

43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/timing.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 34 unchanged lines hidden (view full) ---

43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/timing.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
51#include "debug/Drain.hh"
51#include "debug/ExecFaulting.hh"
52#include "debug/SimpleCPU.hh"
53#include "mem/packet.hh"
54#include "mem/packet_access.hh"
55#include "params/TimingSimpleCPU.hh"
56#include "sim/faults.hh"
57#include "sim/full_system.hh"
58#include "sim/system.hh"

--- 65 unchanged lines hidden (view full) ---

124 // TimingSimpleCPU is ready to drain if it's not waiting for
125 // an access to complete.
126 if (_status == Idle || _status == Running || _status == SwitchedOut) {
127 changeState(SimObject::Drained);
128 return 0;
129 } else {
130 changeState(SimObject::Draining);
131 drainEvent = drain_event;
52#include "debug/ExecFaulting.hh"
53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "params/TimingSimpleCPU.hh"
57#include "sim/faults.hh"
58#include "sim/full_system.hh"
59#include "sim/system.hh"

--- 65 unchanged lines hidden (view full) ---

125 // TimingSimpleCPU is ready to drain if it's not waiting for
126 // an access to complete.
127 if (_status == Idle || _status == Running || _status == SwitchedOut) {
128 changeState(SimObject::Drained);
129 return 0;
130 } else {
131 changeState(SimObject::Draining);
132 drainEvent = drain_event;
133 DPRINTF(Drain, "CPU not drained\n");
132 return 1;
133 }
134}
135
136void
137TimingSimpleCPU::resume()
138{
139 DPRINTF(SimpleCPU, "Resume\n");

--- 684 unchanged lines hidden (view full) ---

824
825 advanceInst(fault);
826}
827
828
829void
830TimingSimpleCPU::completeDrain()
831{
134 return 1;
135 }
136}
137
138void
139TimingSimpleCPU::resume()
140{
141 DPRINTF(SimpleCPU, "Resume\n");

--- 684 unchanged lines hidden (view full) ---

826
827 advanceInst(fault);
828}
829
830
831void
832TimingSimpleCPU::completeDrain()
833{
832 DPRINTF(Config, "Done draining\n");
834 DPRINTF(Drain, "CPU done draining, processing drain event\n");
833 changeState(SimObject::Drained);
834 drainEvent->process();
835}
836
837bool
838TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
839{
840 if (!pkt->wasNacked()) {

--- 120 unchanged lines hidden --- 		835 changeState(SimObject::Drained);
836 drainEvent->process();
837}
838
839bool
840TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
841{
842 if (!pkt->wasNacked()) {

--- 120 unchanged lines hidden ---