timing.cc (8948:e95ee70f876c) timing.cc (8949:3fa1ee293096)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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350 } else {
351 cmd = MemCmd::WriteReq;
352 if (req->isLLSC()) {
353 cmd = MemCmd::StoreCondReq;
354 } else if (req->isSwap()) {
355 cmd = MemCmd::SwapReq;
356 }
357 }
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 341 unchanged lines hidden (view full) ---

350 } else {
351 cmd = MemCmd::WriteReq;
352 if (req->isLLSC()) {
353 cmd = MemCmd::StoreCondReq;
354 } else if (req->isSwap()) {
355 cmd = MemCmd::SwapReq;
356 }
357 }
358 pkt = new Packet(req, cmd, Packet::Broadcast);
358 pkt = new Packet(req, cmd);
359}
360
361void
362TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
363 RequestPtr req1, RequestPtr req2, RequestPtr req,
364 uint8_t *data, bool read)
365{
366 pkt1 = pkt2 = NULL;

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371 buildPacket(pkt1, req, read);
372 return;
373 }
374
375 buildPacket(pkt1, req1, read);
376 buildPacket(pkt2, req2, read);
377
378 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
359}
360
361void
362TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
363 RequestPtr req1, RequestPtr req2, RequestPtr req,
364 uint8_t *data, bool read)
365{
366 pkt1 = pkt2 = NULL;

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371 buildPacket(pkt1, req, read);
372 return;
373 }
374
375 buildPacket(pkt1, req1, read);
376 buildPacket(pkt2, req2, read);
377
378 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
379 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
380 Packet::Broadcast);
379 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
381
382 pkt->dataDynamicArray<uint8_t>(data);
383 pkt1->dataStatic<uint8_t>(data);
384 pkt2->dataStatic<uint8_t>(data + req1->getSize());
385
386 SplitMainSenderState * main_send_state = new SplitMainSenderState;
387 pkt->senderState = main_send_state;
388 main_send_state->fragments[0] = pkt1;

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573
574
575void
576TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
577{
578 if (fault == NoFault) {
579 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
580 req->getVaddr(), req->getPaddr());
380
381 pkt->dataDynamicArray<uint8_t>(data);
382 pkt1->dataStatic<uint8_t>(data);
383 pkt2->dataStatic<uint8_t>(data + req1->getSize());
384
385 SplitMainSenderState * main_send_state = new SplitMainSenderState;
386 pkt->senderState = main_send_state;
387 main_send_state->fragments[0] = pkt1;

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572
573
574void
575TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
576{
577 if (fault == NoFault) {
578 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
579 req->getVaddr(), req->getPaddr());
581 ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
580 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
582 ifetch_pkt->dataStatic(&inst);
583 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
584
585 if (!icachePort.sendTiming(ifetch_pkt)) {
586 // Need to wait for retry
587 _status = IcacheRetry;
588 } else {
589 // Need to wait for cache to respond

--- 374 unchanged lines hidden --- 		581 ifetch_pkt->dataStatic(&inst);
582 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
583
584 if (!icachePort.sendTiming(ifetch_pkt)) {
585 // Need to wait for retry
586 _status = IcacheRetry;
587 } else {
588 // Need to wait for cache to respond

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