timing.cc (8921:e53972f72165) timing.cc (8948:e95ee70f876c)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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713TimingSimpleCPU::IcachePort::ITickEvent::process()
714{
715 cpu->completeIfetch(pkt);
716}
717
718bool
719TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
720{
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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713TimingSimpleCPU::IcachePort::ITickEvent::process()
714{
715 cpu->completeIfetch(pkt);
716}
717
718bool
719TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
720{
721 if (pkt->isResponse() && !pkt->wasNacked()) {
721 assert(pkt->isResponse());
722 if (!pkt->wasNacked()) {
722 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
723 // delay processing of returned data until next CPU clock edge
724 Tick next_tick = cpu->nextCycle(curTick());
725
726 if (next_tick == curTick())
727 cpu->completeIfetch(pkt);
728 else
729 tickEvent.schedule(pkt, next_tick);
730
731 return true;
723 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
724 // delay processing of returned data until next CPU clock edge
725 Tick next_tick = cpu->nextCycle(curTick());
726
727 if (next_tick == curTick())
728 cpu->completeIfetch(pkt);
729 else
730 tickEvent.schedule(pkt, next_tick);
731
732 return true;
732 } else if (pkt->wasNacked()) {
733 } else {
733 assert(cpu->_status == IcacheWaitResponse);
734 pkt->reinitNacked();
735 if (!sendTiming(pkt)) {
736 cpu->_status = IcacheRetry;
737 cpu->ifetch_pkt = pkt;
738 }
739 }
734 assert(cpu->_status == IcacheWaitResponse);
735 pkt->reinitNacked();
736 if (!sendTiming(pkt)) {
737 cpu->_status = IcacheRetry;
738 cpu->ifetch_pkt = pkt;
739 }
740 }
740 //Snooping a Coherence Request, do nothing
741
741 return true;
742}
743
744void
745TimingSimpleCPU::IcachePort::recvRetry()
746{
747 // we shouldn't get a retry unless we have a packet that we're
748 // waiting to transmit

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833 DPRINTF(Config, "Done draining\n");
834 changeState(SimObject::Drained);
835 drainEvent->process();
836}
837
838bool
839TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
840{
742 return true;
743}
744
745void
746TimingSimpleCPU::IcachePort::recvRetry()
747{
748 // we shouldn't get a retry unless we have a packet that we're
749 // waiting to transmit

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834 DPRINTF(Config, "Done draining\n");
835 changeState(SimObject::Drained);
836 drainEvent->process();
837}
838
839bool
840TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
841{
841 if (pkt->isResponse() && !pkt->wasNacked()) {
842 assert(pkt->isResponse());
843 if (!pkt->wasNacked()) {
842 // delay processing of returned data until next CPU clock edge
843 Tick next_tick = cpu->nextCycle(curTick());
844
845 if (next_tick == curTick()) {
846 cpu->completeDataAccess(pkt);
847 } else {
848 if (!tickEvent.scheduled()) {
849 tickEvent.schedule(pkt, next_tick);
850 } else {
851 // In the case of a split transaction and a cache that is
852 // faster than a CPU we could get two responses before
853 // next_tick expires
854 if (!retryEvent.scheduled())
855 cpu->schedule(retryEvent, next_tick);
856 return false;
857 }
858 }
859
860 return true;
844 // delay processing of returned data until next CPU clock edge
845 Tick next_tick = cpu->nextCycle(curTick());
846
847 if (next_tick == curTick()) {
848 cpu->completeDataAccess(pkt);
849 } else {
850 if (!tickEvent.scheduled()) {
851 tickEvent.schedule(pkt, next_tick);
852 } else {
853 // In the case of a split transaction and a cache that is
854 // faster than a CPU we could get two responses before
855 // next_tick expires
856 if (!retryEvent.scheduled())
857 cpu->schedule(retryEvent, next_tick);
858 return false;
859 }
860 }
861
862 return true;
861 }
862 else if (pkt->wasNacked()) {
863 } else {
863 assert(cpu->_status == DcacheWaitResponse);
864 pkt->reinitNacked();
865 if (!sendTiming(pkt)) {
866 cpu->_status = DcacheRetry;
867 cpu->dcache_pkt = pkt;
868 }
869 }
864 assert(cpu->_status == DcacheWaitResponse);
865 pkt->reinitNacked();
866 if (!sendTiming(pkt)) {
867 cpu->_status = DcacheRetry;
868 cpu->dcache_pkt = pkt;
869 }
870 }
870 //Snooping a Coherence Request, do nothing
871
871 return true;
872}
873
874void
875TimingSimpleCPU::DcachePort::DTickEvent::process()
876{
877 cpu->completeDataAccess(pkt);
878}

--- 84 unchanged lines hidden --- 		872 return true;
873}
874
875void
876TimingSimpleCPU::DcachePort::DTickEvent::process()
877{
878 cpu->completeDataAccess(pkt);
879}

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