timing.cc (8779:2a590c51adb1) | timing.cc (8793:5f25086326ac) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72} 73 74void 75TimingSimpleCPU::init() 76{ 77 BaseCPU::init(); 78 if (FullSystem) { 79 for (int i = 0; i < threadContexts.size(); ++i) { | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72} 73 74void 75TimingSimpleCPU::init() 76{ 77 BaseCPU::init(); 78 if (FullSystem) { 79 for (int i = 0; i < threadContexts.size(); ++i) { |
80#if FULL_SYSTEM | |
81 ThreadContext *tc = threadContexts[i]; 82 // initialize CPU, including PC 83 TheISA::initCPU(tc, _cpuId); | 80 ThreadContext *tc = threadContexts[i]; 81 // initialize CPU, including PC 82 TheISA::initCPU(tc, _cpuId); |
84#endif | |
85 } 86 } 87} 88 89Tick 90TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 91{ 92 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); --- 911 unchanged lines hidden (view full) --- 1004//////////////////////////////////////////////////////////////////////// 1005// 1006// TimingSimpleCPU Simulation Object 1007// 1008TimingSimpleCPU * 1009TimingSimpleCPUParams::create() 1010{ 1011 numThreads = 1; | 83 } 84 } 85} 86 87Tick 88TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 89{ 90 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); --- 911 unchanged lines hidden (view full) --- 1002//////////////////////////////////////////////////////////////////////// 1003// 1004// TimingSimpleCPU Simulation Object 1005// 1006TimingSimpleCPU * 1007TimingSimpleCPUParams::create() 1008{ 1009 numThreads = 1; |
1012#if !FULL_SYSTEM | |
1013 if (!FullSystem && workload.size() != 1) 1014 panic("only one workload allowed"); | 1010 if (!FullSystem && workload.size() != 1) 1011 panic("only one workload allowed"); |
1015#endif | |
1016 return new TimingSimpleCPU(this); 1017} | 1012 return new TimingSimpleCPU(this); 1013} |