timing.cc (8707:489489c67fd9) timing.cc (8708:7ccbdea0fa12)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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857 } else {
858 if (!tickEvent.scheduled()) {
859 tickEvent.schedule(pkt, next_tick);
860 } else {
861 // In the case of a split transaction and a cache that is
862 // faster than a CPU we could get two responses before
863 // next_tick expires
864 if (!retryEvent.scheduled())
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 848 unchanged lines hidden (view full) ---

857 } else {
858 if (!tickEvent.scheduled()) {
859 tickEvent.schedule(pkt, next_tick);
860 } else {
861 // In the case of a split transaction and a cache that is
862 // faster than a CPU we could get two responses before
863 // next_tick expires
864 if (!retryEvent.scheduled())
865 schedule(retryEvent, next_tick);
865 cpu->schedule(retryEvent, next_tick);
866 return false;
867 }
868 }
869
870 return true;
871 }
872 else if (pkt->wasNacked()) {
873 assert(cpu->_status == DcacheWaitResponse);

--- 101 unchanged lines hidden --- 		866 return false;
867 }
868 }
869
870 return true;
871 }
872 else if (pkt->wasNacked()) {
873 assert(cpu->_status == DcacheWaitResponse);

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