timing.cc (8706:b1838faf3bcc) | timing.cc (8707:489489c67fd9) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 73 unchanged lines hidden (view full) --- 82 TheISA::initCPU(tc, _cpuId); 83 } 84 85 // Initialise the ThreadContext's memory proxies 86 tcBase()->initMemProxies(tcBase()); 87#endif 88} 89 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 73 unchanged lines hidden (view full) --- 82 TheISA::initCPU(tc, _cpuId); 83 } 84 85 // Initialise the ThreadContext's memory proxies 86 tcBase()->initMemProxies(tcBase()); 87#endif 88} 89 |
90Tick 91TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 92{ 93 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 94 return curTick(); 95} 96 | |
97void | 90void |
98TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) | 91TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) |
99{ | 92{ |
100 //No internal storage to update, jusst return 101 return; 102} 103 104void 105TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 106{ 107 if (status == RangeChange) { 108 if (!snoopRangeSent) { 109 snoopRangeSent = true; 110 sendStatusChange(Port::RangeChange); 111 } 112 return; 113 } 114 115 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 116} 117 118 119void 120TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) 121{ | |
122 pkt = _pkt; 123 cpu->schedule(this, t); 124} 125 126TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) | 93 pkt = _pkt; 94 cpu->schedule(this, t); 95} 96 97TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p) |
127 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock), 128 dcachePort(this, p->clock), fetchEvent(this) | 98 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), 99 dcachePort(this), fetchEvent(this) |
129{ 130 _status = Idle; 131 | 100{ 101 _status = Idle; 102 |
132 icachePort.snoopRangeSent = false; 133 dcachePort.snoopRangeSent = false; 134 | |
135 ifetch_pkt = dcache_pkt = NULL; 136 drainEvent = NULL; 137 previousTick = 0; 138 changeState(SimObject::Running); 139 system->totalNumInsts = 0; 140} 141 142 --- 864 unchanged lines hidden --- | 103 ifetch_pkt = dcache_pkt = NULL; 104 drainEvent = NULL; 105 previousTick = 0; 106 changeState(SimObject::Running); 107 system->totalNumInsts = 0; 108} 109 110 --- 864 unchanged lines hidden --- |