timing.cc (8443:530ff1bc8d70) timing.cc (8444:56de1f9320df)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 418 unchanged lines hidden (view full) ---

427 main_send_state->fragments[0] = pkt1;
428 main_send_state->fragments[1] = pkt2;
429 main_send_state->outstanding = 2;
430 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
431 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
432}
433
434Fault
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 418 unchanged lines hidden (view full) ---

427 main_send_state->fragments[0] = pkt1;
428 main_send_state->fragments[1] = pkt2;
429 main_send_state->outstanding = 2;
430 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
431 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
432}
433
434Fault
435TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
436 unsigned size, unsigned flags)
435TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
436 unsigned size, unsigned flags)
437{
438 Fault fault;
439 const int asid = 0;
440 const ThreadID tid = 0;
441 const Addr pc = thread->instAddr();
442 unsigned block_size = dcachePort.peerBlockSize();
443 BaseTLB::Mode mode = BaseTLB::Read;
444

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495 _status = DcacheWaitResponse;
496 // memory system takes ownership of packet
497 dcache_pkt = NULL;
498 }
499 return dcache_pkt == NULL;
500}
501
502Fault
437{
438 Fault fault;
439 const int asid = 0;
440 const ThreadID tid = 0;
441 const Addr pc = thread->instAddr();
442 unsigned block_size = dcachePort.peerBlockSize();
443 BaseTLB::Mode mode = BaseTLB::Read;
444

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495 _status = DcacheWaitResponse;
496 // memory system takes ownership of packet
497 dcache_pkt = NULL;
498 }
499 return dcache_pkt == NULL;
500}
501
502Fault
503TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
504 Addr addr, unsigned flags, uint64_t *res)
503TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
504 Addr addr, unsigned flags, uint64_t *res)
505{
506 uint8_t *newData = new uint8_t[size];
507 memcpy(newData, data, size);
508
509 const int asid = 0;
510 const ThreadID tid = 0;
511 const Addr pc = thread->instAddr();
512 unsigned block_size = dcachePort.peerBlockSize();

--- 503 unchanged lines hidden --- 		505{
506 uint8_t *newData = new uint8_t[size];
507 memcpy(newData, data, size);
508
509 const int asid = 0;
510 const ThreadID tid = 0;
511 const Addr pc = thread->instAddr();
512 unsigned block_size = dcachePort.peerBlockSize();

--- 503 unchanged lines hidden ---