timing.cc (8276:66bb0d8ae8bf) timing.cc (8277:bfaab04cb292)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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724 TheISA::PCState pcState = thread->pcState();
725 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
726
727 if (needToFetch) {
728 _status = Running;
729 Request *ifetch_req = new Request();
730 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
731 setupFetchRequest(ifetch_req);
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 715 unchanged lines hidden (view full) ---

724 TheISA::PCState pcState = thread->pcState();
725 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
726
727 if (needToFetch) {
728 _status = Running;
729 Request *ifetch_req = new Request();
730 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
731 setupFetchRequest(ifetch_req);
732 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
732 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
733 BaseTLB::Execute);
734 } else {
735 _status = IcacheWaitResponse;
736 completeIfetch(NULL);
737
738 numCycles += tickToCycles(curTick() - previousTick);
739 previousTick = curTick();
740 }
741}
742
743
744void
745TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
746{
747 if (fault == NoFault) {
733 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
734 BaseTLB::Execute);
735 } else {
736 _status = IcacheWaitResponse;
737 completeIfetch(NULL);
738
739 numCycles += tickToCycles(curTick() - previousTick);
740 previousTick = curTick();
741 }
742}
743
744
745void
746TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
747{
748 if (fault == NoFault) {
749 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
750 req->getVaddr(), req->getPaddr());
748 ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
749 ifetch_pkt->dataStatic(&inst);
751 ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
752 ifetch_pkt->dataStatic(&inst);
753 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
750
751 if (!icachePort.sendTiming(ifetch_pkt)) {
752 // Need to wait for retry
753 _status = IcacheRetry;
754 } else {
755 // Need to wait for cache to respond
756 _status = IcacheWaitResponse;
757 // ownership of packet transferred to memory system
758 ifetch_pkt = NULL;
759 }
760 } else {
754
755 if (!icachePort.sendTiming(ifetch_pkt)) {
756 // Need to wait for retry
757 _status = IcacheRetry;
758 } else {
759 // Need to wait for cache to respond
760 _status = IcacheWaitResponse;
761 // ownership of packet transferred to memory system
762 ifetch_pkt = NULL;
763 }
764 } else {
765 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
761 delete req;
762 // fetch fault: advance directly to next instruction (fault handler)
763 _status = Running;
764 advanceInst(fault);
765 }
766
767 numCycles += tickToCycles(curTick() - previousTick);
768 previousTick = curTick();

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795 fetch();
796 }
797}
798
799
800void
801TimingSimpleCPU::completeIfetch(PacketPtr pkt)
802{
766 delete req;
767 // fetch fault: advance directly to next instruction (fault handler)
768 _status = Running;
769 advanceInst(fault);
770 }
771
772 numCycles += tickToCycles(curTick() - previousTick);
773 previousTick = curTick();

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800 fetch();
801 }
802}
803
804
805void
806TimingSimpleCPU::completeIfetch(PacketPtr pkt)
807{
808 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
809 pkt->getAddr() : 0);
810
803 // received a response from the icache: execute the received
804 // instruction
805
806 assert(!pkt || !pkt->isError());
807 assert(_status == IcacheWaitResponse);
808
809 _status = Running;
810

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876{
877 cpu->completeIfetch(pkt);
878}
879
880bool
881TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
882{
883 if (pkt->isResponse() && !pkt->wasNacked()) {
811 // received a response from the icache: execute the received
812 // instruction
813
814 assert(!pkt || !pkt->isError());
815 assert(_status == IcacheWaitResponse);
816
817 _status = Running;
818

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884{
885 cpu->completeIfetch(pkt);
886}
887
888bool
889TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
890{
891 if (pkt->isResponse() && !pkt->wasNacked()) {
892 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
884 // delay processing of returned data until next CPU clock edge
885 Tick next_tick = cpu->nextCycle(curTick());
886
887 if (next_tick == curTick())
888 cpu->completeIfetch(pkt);
889 else
890 tickEvent.schedule(pkt, next_tick);
891

--- 246 unchanged lines hidden --- 		893 // delay processing of returned data until next CPU clock edge
894 Tick next_tick = cpu->nextCycle(curTick());
895
896 if (next_tick == curTick())
897 cpu->completeIfetch(pkt);
898 else
899 tickEvent.schedule(pkt, next_tick);
900

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