timing.cc (8232:b28d06a175be) timing.cc (8276:66bb0d8ae8bf)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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720 // We must have just got suspended by a PC event
721 if (_status == Idle)
722 return;
723
724 TheISA::PCState pcState = thread->pcState();
725 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
726
727 if (needToFetch) {
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 711 unchanged lines hidden (view full) ---

720 // We must have just got suspended by a PC event
721 if (_status == Idle)
722 return;
723
724 TheISA::PCState pcState = thread->pcState();
725 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
726
727 if (needToFetch) {
728 _status = Running;
728 Request *ifetch_req = new Request();
729 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
730 setupFetchRequest(ifetch_req);
731 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
732 BaseTLB::Execute);
733 } else {
734 _status = IcacheWaitResponse;
735 completeIfetch(NULL);

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766 numCycles += tickToCycles(curTick() - previousTick);
767 previousTick = curTick();
768}
769
770
771void
772TimingSimpleCPU::advanceInst(Fault fault)
773{
729 Request *ifetch_req = new Request();
730 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
731 setupFetchRequest(ifetch_req);
732 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
733 BaseTLB::Execute);
734 } else {
735 _status = IcacheWaitResponse;
736 completeIfetch(NULL);

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767 numCycles += tickToCycles(curTick() - previousTick);
768 previousTick = curTick();
769}
770
771
772void
773TimingSimpleCPU::advanceInst(Fault fault)
774{
774 if (fault != NoFault || !stayAtPC)
775
776 if (_status == Faulting)
777 return;
778
779 if (fault != NoFault) {
775 advancePC(fault);
780 advancePC(fault);
781 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
782 reschedule(fetchEvent, nextCycle(), true);
783 _status = Faulting;
784 return;
785 }
776
786
787
788 if (!stayAtPC)
789 advancePC(fault);
790
777 if (_status == Running) {
778 // kick off fetch of next instruction... callback from icache
779 // response will cause that instruction to be executed,
780 // keeping the CPU running.
781 fetch();
782 }
783}
784
785
786void
787TimingSimpleCPU::completeIfetch(PacketPtr pkt)
788{
791 if (_status == Running) {
792 // kick off fetch of next instruction... callback from icache
793 // response will cause that instruction to be executed,
794 // keeping the CPU running.
795 fetch();
796 }
797}
798
799
800void
801TimingSimpleCPU::completeIfetch(PacketPtr pkt)
802{
789 DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
790
791 // received a response from the icache: execute the received
792 // instruction
793
794 assert(!pkt || !pkt->isError());
795 assert(_status == IcacheWaitResponse);
796
797 _status = Running;
798

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873 Tick next_tick = cpu->nextCycle(curTick());
874
875 if (next_tick == curTick())
876 cpu->completeIfetch(pkt);
877 else
878 tickEvent.schedule(pkt, next_tick);
879
880 return true;
803 // received a response from the icache: execute the received
804 // instruction
805
806 assert(!pkt || !pkt->isError());
807 assert(_status == IcacheWaitResponse);
808
809 _status = Running;
810

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885 Tick next_tick = cpu->nextCycle(curTick());
886
887 if (next_tick == curTick())
888 cpu->completeIfetch(pkt);
889 else
890 tickEvent.schedule(pkt, next_tick);
891
892 return true;
881 }
882 else if (pkt->wasNacked()) {
893 } else if (pkt->wasNacked()) {
883 assert(cpu->_status == IcacheWaitResponse);
884 pkt->reinitNacked();
885 if (!sendTiming(pkt)) {
886 cpu->_status = IcacheRetry;
887 cpu->ifetch_pkt = pkt;
888 }
889 }
890 //Snooping a Coherence Request, do nothing

--- 236 unchanged lines hidden --- 		894 assert(cpu->_status == IcacheWaitResponse);
895 pkt->reinitNacked();
896 if (!sendTiming(pkt)) {
897 cpu->_status = IcacheRetry;
898 cpu->ifetch_pkt = pkt;
899 }
900 }
901 //Snooping a Coherence Request, do nothing

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