timing.cc (7945:32758425de8c) timing.cc (8105:906864dd0937)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 27 unchanged lines hidden (view full) ---

36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 27 unchanged lines hidden (view full) ---

36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmaped_ipr.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/simple/timing.hh"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "params/TimingSimpleCPU.hh"

--- 206 unchanged lines hidden (view full) ---

259 notIdleFraction--;
260 _status = Idle;
261}
262
263bool
264TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
265{
266 RequestPtr req = pkt->req;
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/simple/timing.hh"
50#include "mem/packet.hh"
51#include "mem/packet_access.hh"
52#include "params/TimingSimpleCPU.hh"

--- 206 unchanged lines hidden (view full) ---

259 notIdleFraction--;
260 _status = Idle;
261}
262
263bool
264TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
265{
266 RequestPtr req = pkt->req;
267 if (req->isMmapedIpr()) {
267 if (req->isMmappedIpr()) {
268 Tick delay;
269 delay = TheISA::handleIprRead(thread->getTC(), pkt);
270 new IprEvent(pkt, this, nextCycle(curTick() + delay));
271 _status = DcacheWaitResponse;
272 dcache_pkt = NULL;
273 } else if (!dcachePort.sendTiming(pkt)) {
274 _status = DcacheRetry;
275 dcache_pkt = pkt;

--- 120 unchanged lines hidden (view full) ---

396
397void
398TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
399 RequestPtr req1, RequestPtr req2, RequestPtr req,
400 uint8_t *data, bool read)
401{
402 pkt1 = pkt2 = NULL;
403
268 Tick delay;
269 delay = TheISA::handleIprRead(thread->getTC(), pkt);
270 new IprEvent(pkt, this, nextCycle(curTick() + delay));
271 _status = DcacheWaitResponse;
272 dcache_pkt = NULL;
273 } else if (!dcachePort.sendTiming(pkt)) {
274 _status = DcacheRetry;
275 dcache_pkt = pkt;

--- 120 unchanged lines hidden (view full) ---

396
397void
398TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
399 RequestPtr req1, RequestPtr req2, RequestPtr req,
400 uint8_t *data, bool read)
401{
402 pkt1 = pkt2 = NULL;
403
404 assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
404 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
405
406 if (req->getFlags().isSet(Request::NO_ACCESS)) {
407 buildPacket(pkt1, req, read);
408 return;
409 }
410
411 buildPacket(pkt1, req1, read);
412 buildPacket(pkt2, req2, read);

--- 118 unchanged lines hidden (view full) ---

531{
532 return read(addr, (uint32_t&)data, flags);
533}
534
535bool
536TimingSimpleCPU::handleWritePacket()
537{
538 RequestPtr req = dcache_pkt->req;
405
406 if (req->getFlags().isSet(Request::NO_ACCESS)) {
407 buildPacket(pkt1, req, read);
408 return;
409 }
410
411 buildPacket(pkt1, req1, read);
412 buildPacket(pkt2, req2, read);

--- 118 unchanged lines hidden (view full) ---

531{
532 return read(addr, (uint32_t&)data, flags);
533}
534
535bool
536TimingSimpleCPU::handleWritePacket()
537{
538 RequestPtr req = dcache_pkt->req;
539 if (req->isMmapedIpr()) {
539 if (req->isMmappedIpr()) {
540 Tick delay;
541 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
542 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
543 _status = DcacheWaitResponse;
544 dcache_pkt = NULL;
545 } else if (!dcachePort.sendTiming(dcache_pkt)) {
546 _status = DcacheRetry;
547 } else {

--- 572 unchanged lines hidden --- 		540 Tick delay;
541 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
542 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
543 _status = DcacheWaitResponse;
544 dcache_pkt = NULL;
545 } else if (!dcachePort.sendTiming(dcache_pkt)) {
546 _status = DcacheRetry;
547 } else {

--- 572 unchanged lines hidden ---