timing.cc (7911:267e1e16e51b) timing.cc (7945:32758425de8c)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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747 // Need to wait for cache to respond
748 _status = IcacheWaitResponse;
749 // ownership of packet transferred to memory system
750 ifetch_pkt = NULL;
751 }
752 } else {
753 delete req;
754 // fetch fault: advance directly to next instruction (fault handler)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 738 unchanged lines hidden (view full) ---

747 // Need to wait for cache to respond
748 _status = IcacheWaitResponse;
749 // ownership of packet transferred to memory system
750 ifetch_pkt = NULL;
751 }
752 } else {
753 delete req;
754 // fetch fault: advance directly to next instruction (fault handler)
755 _status = Running;
755 advanceInst(fault);
756 }
757
758 numCycles += tickToCycles(curTick() - previousTick);
759 previousTick = curTick();
760}
761
762

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800 completeDrain();
801 return;
802 }
803
804 preExecute();
805 if (curStaticInst && curStaticInst->isMemRef()) {
806 // load or store: just send to dcache
807 Fault fault = curStaticInst->initiateAcc(this, traceData);
756 advanceInst(fault);
757 }
758
759 numCycles += tickToCycles(curTick() - previousTick);
760 previousTick = curTick();
761}
762
763

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801 completeDrain();
802 return;
803 }
804
805 preExecute();
806 if (curStaticInst && curStaticInst->isMemRef()) {
807 // load or store: just send to dcache
808 Fault fault = curStaticInst->initiateAcc(this, traceData);
808 if (_status != Running) {
809 // instruction will complete in dcache response callback
810 assert(_status == DcacheWaitResponse ||
811 _status == DcacheRetry || DTBWaitResponse);
812 assert(fault == NoFault);
813 } else {
809
810 // If we're not running now the instruction will complete in a dcache
811 // response callback or the instruction faulted and has started an
812 // ifetch
813 if (_status == Running) {
814 if (fault != NoFault && traceData) {
815 // If there was a fault, we shouldn't trace this instruction.
816 delete traceData;
817 traceData = NULL;
818 }
819
820 postExecute();
821 // @todo remove me after debugging with legion done

--- 298 unchanged lines hidden --- 		814 if (fault != NoFault && traceData) {
815 // If there was a fault, we shouldn't trace this instruction.
816 delete traceData;
817 traceData = NULL;
818 }
819
820 postExecute();
821 // @todo remove me after debugging with legion done

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