timing.cc (7745:434b5dfb87d9) timing.cc (7823:dac01f14f20f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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80 }
81#endif
82}
83
84Tick
85TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
86{
87 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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80 }
81#endif
82}
83
84Tick
85TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
86{
87 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
88 return curTick;
88 return curTick();
89}
90
91void
92TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
93{
94 //No internal storage to update, jusst return
95 return;
96}

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184 changeState(SimObject::Running);
185}
186
187void
188TimingSimpleCPU::switchOut()
189{
190 assert(_status == Running || _status == Idle);
191 _status = SwitchedOut;
89}
90
91void
92TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
93{
94 //No internal storage to update, jusst return
95 return;
96}

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184 changeState(SimObject::Running);
185}
186
187void
188TimingSimpleCPU::switchOut()
189{
190 assert(_status == Running || _status == Idle);
191 _status = SwitchedOut;
192 numCycles += tickToCycles(curTick - previousTick);
192 numCycles += tickToCycles(curTick() - previousTick);
193
194 // If we've been scheduled to resume but are then told to switch out,
195 // we'll need to cancel it.
196 if (fetchEvent.scheduled())
197 deschedule(fetchEvent);
198}
199
200

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212 break;
213 }
214 }
215
216 if (_status != Running) {
217 _status = Idle;
218 }
219 assert(threadContexts.size() == 1);
193
194 // If we've been scheduled to resume but are then told to switch out,
195 // we'll need to cancel it.
196 if (fetchEvent.scheduled())
197 deschedule(fetchEvent);
198}
199
200

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212 break;
213 }
214 }
215
216 if (_status != Running) {
217 _status = Idle;
218 }
219 assert(threadContexts.size() == 1);
220 previousTick = curTick;
220 previousTick = curTick();
221}
222
223
224void
225TimingSimpleCPU::activateContext(int thread_num, int delay)
226{
227 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
228
229 assert(thread_num == 0);
230 assert(thread);
231
232 assert(_status == Idle);
233
234 notIdleFraction++;
235 _status = Running;
236
237 // kick things off by initiating the fetch of the next instruction
221}
222
223
224void
225TimingSimpleCPU::activateContext(int thread_num, int delay)
226{
227 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
228
229 assert(thread_num == 0);
230 assert(thread);
231
232 assert(_status == Idle);
233
234 notIdleFraction++;
235 _status = Running;
236
237 // kick things off by initiating the fetch of the next instruction
238 schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
238 schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
239}
240
241
242void
243TimingSimpleCPU::suspendContext(int thread_num)
244{
245 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
246

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261
262bool
263TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
264{
265 RequestPtr req = pkt->req;
266 if (req->isMmapedIpr()) {
267 Tick delay;
268 delay = TheISA::handleIprRead(thread->getTC(), pkt);
239}
240
241
242void
243TimingSimpleCPU::suspendContext(int thread_num)
244{
245 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
246

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261
262bool
263TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
264{
265 RequestPtr req = pkt->req;
266 if (req->isMmapedIpr()) {
267 Tick delay;
268 delay = TheISA::handleIprRead(thread->getTC(), pkt);
269 new IprEvent(pkt, this, nextCycle(curTick + delay));
269 new IprEvent(pkt, this, nextCycle(curTick() + delay));
270 _status = DcacheWaitResponse;
271 dcache_pkt = NULL;
272 } else if (!dcachePort.sendTiming(pkt)) {
273 _status = DcacheRetry;
274 dcache_pkt = pkt;
275 } else {
276 _status = DcacheWaitResponse;
277 // memory system takes ownership of packet

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350 }
351}
352
353void
354TimingSimpleCPU::translationFault(Fault fault)
355{
356 // fault may be NoFault in cases where a fault is suppressed,
357 // for instance prefetches.
270 _status = DcacheWaitResponse;
271 dcache_pkt = NULL;
272 } else if (!dcachePort.sendTiming(pkt)) {
273 _status = DcacheRetry;
274 dcache_pkt = pkt;
275 } else {
276 _status = DcacheWaitResponse;
277 // memory system takes ownership of packet

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350 }
351}
352
353void
354TimingSimpleCPU::translationFault(Fault fault)
355{
356 // fault may be NoFault in cases where a fault is suppressed,
357 // for instance prefetches.
358 numCycles += tickToCycles(curTick - previousTick);
359 previousTick = curTick;
358 numCycles += tickToCycles(curTick() - previousTick);
359 previousTick = curTick();
360
361 if (traceData) {
362 // Since there was a fault, we shouldn't trace this instruction.
363 delete traceData;
364 traceData = NULL;
365 }
366
367 postExecute();

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533
534bool
535TimingSimpleCPU::handleWritePacket()
536{
537 RequestPtr req = dcache_pkt->req;
538 if (req->isMmapedIpr()) {
539 Tick delay;
540 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
360
361 if (traceData) {
362 // Since there was a fault, we shouldn't trace this instruction.
363 delete traceData;
364 traceData = NULL;
365 }
366
367 postExecute();

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533
534bool
535TimingSimpleCPU::handleWritePacket()
536{
537 RequestPtr req = dcache_pkt->req;
538 if (req->isMmapedIpr()) {
539 Tick delay;
540 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
541 new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
541 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
542 _status = DcacheWaitResponse;
543 dcache_pkt = NULL;
544 } else if (!dcachePort.sendTiming(dcache_pkt)) {
545 _status = DcacheRetry;
546 } else {
547 _status = DcacheWaitResponse;
548 // memory system takes ownership of packet
549 dcache_pkt = NULL;

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721 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
722 setupFetchRequest(ifetch_req);
723 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
724 BaseTLB::Execute);
725 } else {
726 _status = IcacheWaitResponse;
727 completeIfetch(NULL);
728
542 _status = DcacheWaitResponse;
543 dcache_pkt = NULL;
544 } else if (!dcachePort.sendTiming(dcache_pkt)) {
545 _status = DcacheRetry;
546 } else {
547 _status = DcacheWaitResponse;
548 // memory system takes ownership of packet
549 dcache_pkt = NULL;

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721 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
722 setupFetchRequest(ifetch_req);
723 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
724 BaseTLB::Execute);
725 } else {
726 _status = IcacheWaitResponse;
727 completeIfetch(NULL);
728
729 numCycles += tickToCycles(curTick - previousTick);
730 previousTick = curTick;
729 numCycles += tickToCycles(curTick() - previousTick);
730 previousTick = curTick();
731 }
732}
733
734
735void
736TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
737{
738 if (fault == NoFault) {

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749 ifetch_pkt = NULL;
750 }
751 } else {
752 delete req;
753 // fetch fault: advance directly to next instruction (fault handler)
754 advanceInst(fault);
755 }
756
731 }
732}
733
734
735void
736TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
737{
738 if (fault == NoFault) {

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749 ifetch_pkt = NULL;
750 }
751 } else {
752 delete req;
753 // fetch fault: advance directly to next instruction (fault handler)
754 advanceInst(fault);
755 }
756
757 numCycles += tickToCycles(curTick - previousTick);
758 previousTick = curTick;
757 numCycles += tickToCycles(curTick() - previousTick);
758 previousTick = curTick();
759}
760
761
762void
763TimingSimpleCPU::advanceInst(Fault fault)
764{
765 if (fault != NoFault || !stayAtPC)
766 advancePC(fault);

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782 // received a response from the icache: execute the received
783 // instruction
784
785 assert(!pkt || !pkt->isError());
786 assert(_status == IcacheWaitResponse);
787
788 _status = Running;
789
759}
760
761
762void
763TimingSimpleCPU::advanceInst(Fault fault)
764{
765 if (fault != NoFault || !stayAtPC)
766 advancePC(fault);

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782 // received a response from the icache: execute the received
783 // instruction
784
785 assert(!pkt || !pkt->isError());
786 assert(_status == IcacheWaitResponse);
787
788 _status = Running;
789
790 numCycles += tickToCycles(curTick - previousTick);
791 previousTick = curTick;
790 numCycles += tickToCycles(curTick() - previousTick);
791 previousTick = curTick();
792
793 if (getState() == SimObject::Draining) {
794 if (pkt) {
795 delete pkt->req;
796 delete pkt;
797 }
798
799 completeDrain();

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857 cpu->completeIfetch(pkt);
858}
859
860bool
861TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
862{
863 if (pkt->isResponse() && !pkt->wasNacked()) {
864 // delay processing of returned data until next CPU clock edge
792
793 if (getState() == SimObject::Draining) {
794 if (pkt) {
795 delete pkt->req;
796 delete pkt;
797 }
798
799 completeDrain();

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857 cpu->completeIfetch(pkt);
858}
859
860bool
861TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
862{
863 if (pkt->isResponse() && !pkt->wasNacked()) {
864 // delay processing of returned data until next CPU clock edge
865 Tick next_tick = cpu->nextCycle(curTick);
865 Tick next_tick = cpu->nextCycle(curTick());
866
866
867 if (next_tick == curTick)
867 if (next_tick == curTick())
868 cpu->completeIfetch(pkt);
869 else
870 tickEvent.schedule(pkt, next_tick);
871
872 return true;
873 }
874 else if (pkt->wasNacked()) {
875 assert(cpu->_status == IcacheWaitResponse);

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901TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
902{
903 // received a response from the dcache: complete the load or store
904 // instruction
905 assert(!pkt->isError());
906 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
907 pkt->req->getFlags().isSet(Request::NO_ACCESS));
908
868 cpu->completeIfetch(pkt);
869 else
870 tickEvent.schedule(pkt, next_tick);
871
872 return true;
873 }
874 else if (pkt->wasNacked()) {
875 assert(cpu->_status == IcacheWaitResponse);

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901TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
902{
903 // received a response from the dcache: complete the load or store
904 // instruction
905 assert(!pkt->isError());
906 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
907 pkt->req->getFlags().isSet(Request::NO_ACCESS));
908
909 numCycles += tickToCycles(curTick - previousTick);
910 previousTick = curTick;
909 numCycles += tickToCycles(curTick() - previousTick);
910 previousTick = curTick();
911
912 if (pkt->senderState) {
913 SplitFragmentSenderState * send_state =
914 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
915 assert(send_state);
916 delete pkt->req;
917 delete pkt;
918 PacketPtr big_pkt = send_state->bigPkt;

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989#endif
990}
991
992bool
993TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
994{
995 if (pkt->isResponse() && !pkt->wasNacked()) {
996 // delay processing of returned data until next CPU clock edge
911
912 if (pkt->senderState) {
913 SplitFragmentSenderState * send_state =
914 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
915 assert(send_state);
916 delete pkt->req;
917 delete pkt;
918 PacketPtr big_pkt = send_state->bigPkt;

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989#endif
990}
991
992bool
993TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
994{
995 if (pkt->isResponse() && !pkt->wasNacked()) {
996 // delay processing of returned data until next CPU clock edge
997 Tick next_tick = cpu->nextCycle(curTick);
997 Tick next_tick = cpu->nextCycle(curTick());
998
998
999 if (next_tick == curTick) {
999 if (next_tick == curTick()) {
1000 cpu->completeDataAccess(pkt);
1001 } else {
1002 if (!tickEvent.scheduled()) {
1003 tickEvent.schedule(pkt, next_tick);
1004 } else {
1005 // In the case of a split transaction and a cache that is
1006 // faster than a CPU we could get two responses before
1007 // next_tick expires

--- 111 unchanged lines hidden --- 		1000 cpu->completeDataAccess(pkt);
1001 } else {
1002 if (!tickEvent.scheduled()) {
1003 tickEvent.schedule(pkt, next_tick);
1004 } else {
1005 // In the case of a split transaction and a cache that is
1006 // faster than a CPU we could get two responses before
1007 // next_tick expires

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