timing.cc (7691:358c00c482f7) timing.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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417
418Fault
419TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
420 unsigned size, unsigned flags)
421{
422 Fault fault;
423 const int asid = 0;
424 const ThreadID tid = 0;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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417
418Fault
419TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
420 unsigned size, unsigned flags)
421{
422 Fault fault;
423 const int asid = 0;
424 const ThreadID tid = 0;
425 const Addr pc = thread->readPC();
425 const Addr pc = thread->instAddr();
426 unsigned block_size = dcachePort.peerBlockSize();
427 BaseTLB::Mode mode = BaseTLB::Read;
428
429 if (traceData) {
430 traceData->setAddr(addr);
431 }
432
433 RequestPtr req = new Request(asid, addr, size,

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540}
541
542Fault
543TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
544 Addr addr, unsigned flags, uint64_t *res)
545{
546 const int asid = 0;
547 const ThreadID tid = 0;
426 unsigned block_size = dcachePort.peerBlockSize();
427 BaseTLB::Mode mode = BaseTLB::Read;
428
429 if (traceData) {
430 traceData->setAddr(addr);
431 }
432
433 RequestPtr req = new Request(asid, addr, size,

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540}
541
542Fault
543TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
544 Addr addr, unsigned flags, uint64_t *res)
545{
546 const int asid = 0;
547 const ThreadID tid = 0;
548 const Addr pc = thread->readPC();
548 const Addr pc = thread->instAddr();
549 unsigned block_size = dcachePort.peerBlockSize();
550 BaseTLB::Mode mode = BaseTLB::Write;
551
552 if (traceData) {
553 traceData->setAddr(addr);
554 }
555
556 RequestPtr req = new Request(asid, addr, size,

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696{
697 DPRINTF(SimpleCPU, "Fetch\n");
698
699 if (!curStaticInst || !curStaticInst->isDelayedCommit())
700 checkForInterrupts();
701
702 checkPcEventQueue();
703
549 unsigned block_size = dcachePort.peerBlockSize();
550 BaseTLB::Mode mode = BaseTLB::Write;
551
552 if (traceData) {
553 traceData->setAddr(addr);
554 }
555
556 RequestPtr req = new Request(asid, addr, size,

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696{
697 DPRINTF(SimpleCPU, "Fetch\n");
698
699 if (!curStaticInst || !curStaticInst->isDelayedCommit())
700 checkForInterrupts();
701
702 checkPcEventQueue();
703
704 bool fromRom = isRomMicroPC(thread->readMicroPC());
704 TheISA::PCState pcState = thread->pcState();
705 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
705
706
706 if (!fromRom && !curMacroStaticInst) {
707 if (needToFetch) {
707 Request *ifetch_req = new Request();
708 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
709 setupFetchRequest(ifetch_req);
710 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
711 BaseTLB::Execute);
712 } else {
713 _status = IcacheWaitResponse;
714 completeIfetch(NULL);

--- 383 unchanged lines hidden --- 		708 Request *ifetch_req = new Request();
709 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
710 setupFetchRequest(ifetch_req);
711 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
712 BaseTLB::Execute);
713 } else {
714 _status = IcacheWaitResponse;
715 completeIfetch(NULL);

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