timing.cc (7678:f19b6a3a8cec) | timing.cc (7691:358c00c482f7) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 260 unchanged lines hidden (view full) --- 269} 270 271void 272TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 273 bool read) 274{ 275 PacketPtr pkt; 276 buildPacket(pkt, req, read); | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 260 unchanged lines hidden (view full) --- 269} 270 271void 272TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, 273 bool read) 274{ 275 PacketPtr pkt; 276 buildPacket(pkt, req, read); |
277 pkt->dataDynamic | 277 pkt->dataDynamicArray<uint8_t>(data); |
278 if (req->getFlags().isSet(Request::NO_ACCESS)) { 279 assert(!dcache_pkt); 280 pkt->makeResponse(); 281 completeDataAccess(pkt); 282 } else if (read) { 283 handleReadPacket(pkt); 284 } else { 285 bool do_access = true; // flag to suppress cache access --- 111 unchanged lines hidden (view full) --- 397 398 buildPacket(pkt1, req1, read); 399 buildPacket(pkt2, req2, read); 400 401 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 402 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 403 Packet::Broadcast); 404 | 278 if (req->getFlags().isSet(Request::NO_ACCESS)) { 279 assert(!dcache_pkt); 280 pkt->makeResponse(); 281 completeDataAccess(pkt); 282 } else if (read) { 283 handleReadPacket(pkt); 284 } else { 285 bool do_access = true; // flag to suppress cache access --- 111 unchanged lines hidden (view full) --- 397 398 buildPacket(pkt1, req1, read); 399 buildPacket(pkt2, req2, read); 400 401 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); 402 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 403 Packet::Broadcast); 404 |
405 pkt->dataDynamic | 405 pkt->dataDynamicArray<uint8_t>(data); |
406 pkt1->dataStatic<uint8_t>(data); 407 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 408 409 SplitMainSenderState * main_send_state = new SplitMainSenderState; 410 pkt->senderState = main_send_state; 411 main_send_state->fragments[0] = pkt1; 412 main_send_state->fragments[1] = pkt2; 413 main_send_state->outstanding = 2; --- 183 unchanged lines hidden (view full) --- 597 598template <class T> 599Fault 600TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 601{ 602 if (traceData) { 603 traceData->setData(data); 604 } | 406 pkt1->dataStatic<uint8_t>(data); 407 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 408 409 SplitMainSenderState * main_send_state = new SplitMainSenderState; 410 pkt->senderState = main_send_state; 411 main_send_state->fragments[0] = pkt1; 412 main_send_state->fragments[1] = pkt2; 413 main_send_state->outstanding = 2; --- 183 unchanged lines hidden (view full) --- 597 598template <class T> 599Fault 600TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 601{ 602 if (traceData) { 603 traceData->setData(data); 604 } |
605 T *dataP = new T; | 605 T *dataP = (T*) new uint8_t[sizeof(T)]; |
606 *dataP = TheISA::htog(data); 607 608 return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 609} 610 611 612#ifndef DOXYGEN_SHOULD_SKIP_THIS 613template --- 55 unchanged lines hidden (view full) --- 669TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 670{ 671 _status = Running; 672 673 if (state->getFault() != NoFault) { 674 if (state->isPrefetch()) { 675 state->setNoFault(); 676 } | 606 *dataP = TheISA::htog(data); 607 608 return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res); 609} 610 611 612#ifndef DOXYGEN_SHOULD_SKIP_THIS 613template --- 55 unchanged lines hidden (view full) --- 669TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 670{ 671 _status = Running; 672 673 if (state->getFault() != NoFault) { 674 if (state->isPrefetch()) { 675 state->setNoFault(); 676 } |
677 delete state->data; | 677 delete [] state->data; |
678 state->deleteReqs(); 679 translationFault(state->getFault()); 680 } else { 681 if (!state->isSplit) { 682 sendData(state->mainReq, state->data, state->res, 683 state->mode == BaseTLB::Read); 684 } else { 685 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, --- 412 unchanged lines hidden --- | 678 state->deleteReqs(); 679 translationFault(state->getFault()); 680 } else { 681 if (!state->isSplit) { 682 sendData(state->mainReq, state->data, state->res, 683 state->mode == BaseTLB::Read); 684 } else { 685 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq, --- 412 unchanged lines hidden --- |