timing.cc (7016:8b2b8e5e7d35) timing.cc (7045:e21fe6a62b1c)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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421 Fault fault;
422 const int asid = 0;
423 const ThreadID tid = 0;
424 const Addr pc = thread->readPC();
425 unsigned block_size = dcachePort.peerBlockSize();
426 int data_size = sizeof(T);
427 BaseTLB::Mode mode = BaseTLB::Read;
428
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 412 unchanged lines hidden (view full) ---

421 Fault fault;
422 const int asid = 0;
423 const ThreadID tid = 0;
424 const Addr pc = thread->readPC();
425 unsigned block_size = dcachePort.peerBlockSize();
426 int data_size = sizeof(T);
427 BaseTLB::Mode mode = BaseTLB::Read;
428
429 if (traceData) {
430 traceData->setAddr(addr);
431 }
432
429 RequestPtr req = new Request(asid, addr, data_size,
430 flags, pc, _cpuId, tid);
431
432 Addr split_addr = roundDown(addr + data_size - 1, block_size);
433 assert(split_addr <= addr || split_addr - addr < block_size);
434
435 // This will need a new way to tell if it's hooked up to a cache or not.
436 if (req->isUncacheable())

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455 } else {
456 WholeTranslationState *state =
457 new WholeTranslationState(req, (uint8_t *)(new T), NULL, mode);
458 DataTranslation<TimingSimpleCPU> *translation
459 = new DataTranslation<TimingSimpleCPU>(this, state);
460 thread->dtb->translateTiming(req, tc, translation, mode);
461 }
462
433 RequestPtr req = new Request(asid, addr, data_size,
434 flags, pc, _cpuId, tid);
435
436 Addr split_addr = roundDown(addr + data_size - 1, block_size);
437 assert(split_addr <= addr || split_addr - addr < block_size);
438
439 // This will need a new way to tell if it's hooked up to a cache or not.
440 if (req->isUncacheable())

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459 } else {
460 WholeTranslationState *state =
461 new WholeTranslationState(req, (uint8_t *)(new T), NULL, mode);
462 DataTranslation<TimingSimpleCPU> *translation
463 = new DataTranslation<TimingSimpleCPU>(this, state);
464 thread->dtb->translateTiming(req, tc, translation, mode);
465 }
466
463 if (traceData) {
464 traceData->setData(data);
465 traceData->setAddr(addr);
466 }
467
468 return NoFault;
469}
470
471#ifndef DOXYGEN_SHOULD_SKIP_THIS
472
473template
474Fault
475TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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543{
544 const int asid = 0;
545 const ThreadID tid = 0;
546 const Addr pc = thread->readPC();
547 unsigned block_size = dcachePort.peerBlockSize();
548 int data_size = sizeof(T);
549 BaseTLB::Mode mode = BaseTLB::Write;
550
467 return NoFault;
468}
469
470#ifndef DOXYGEN_SHOULD_SKIP_THIS
471
472template
473Fault
474TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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542{
543 const int asid = 0;
544 const ThreadID tid = 0;
545 const Addr pc = thread->readPC();
546 unsigned block_size = dcachePort.peerBlockSize();
547 int data_size = sizeof(T);
548 BaseTLB::Mode mode = BaseTLB::Write;
549
550 if (traceData) {
551 traceData->setAddr(addr);
552 traceData->setData(data);
553 }
554
551 RequestPtr req = new Request(asid, addr, data_size,
552 flags, pc, _cpuId, tid);
553
554 Addr split_addr = roundDown(addr + data_size - 1, block_size);
555 assert(split_addr <= addr || split_addr - addr < block_size);
556
557 // This will need a new way to tell if it's hooked up to a cache or not.
558 if (req->isUncacheable())

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579 } else {
580 WholeTranslationState *state =
581 new WholeTranslationState(req, (uint8_t *)dataP, res, mode);
582 DataTranslation<TimingSimpleCPU> *translation =
583 new DataTranslation<TimingSimpleCPU>(this, state);
584 thread->dtb->translateTiming(req, tc, translation, mode);
585 }
586
555 RequestPtr req = new Request(asid, addr, data_size,
556 flags, pc, _cpuId, tid);
557
558 Addr split_addr = roundDown(addr + data_size - 1, block_size);
559 assert(split_addr <= addr || split_addr - addr < block_size);
560
561 // This will need a new way to tell if it's hooked up to a cache or not.
562 if (req->isUncacheable())

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583 } else {
584 WholeTranslationState *state =
585 new WholeTranslationState(req, (uint8_t *)dataP, res, mode);
586 DataTranslation<TimingSimpleCPU> *translation =
587 new DataTranslation<TimingSimpleCPU>(this, state);
588 thread->dtb->translateTiming(req, tc, translation, mode);
589 }
590
587 if (traceData) {
588 traceData->setAddr(req->getVaddr());
589 traceData->setData(data);
590 }
591
592 // If the write needs to have a fault on the access, consider calling
593 // changeStatus() and changing it to "bad addr write" or something.
591 // Translation faults will be returned via finishTranslation()
594 return NoFault;
595}
596
597
598#ifndef DOXYGEN_SHOULD_SKIP_THIS
599template
600Fault
601TimingSimpleCPU::write(Twin32_t data, Addr addr,

--- 482 unchanged lines hidden --- 		592 return NoFault;
593}
594
595
596#ifndef DOXYGEN_SHOULD_SKIP_THIS
597template
598Fault
599TimingSimpleCPU::write(Twin32_t data, Addr addr,

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