timing.cc (6973:a123bd350935) timing.cc (7016:8b2b8e5e7d35)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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427 BaseTLB::Mode mode = BaseTLB::Read;
428
429 RequestPtr req = new Request(asid, addr, data_size,
430 flags, pc, _cpuId, tid);
431
432 Addr split_addr = roundDown(addr + data_size - 1, block_size);
433 assert(split_addr <= addr || split_addr - addr < block_size);
434
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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427 BaseTLB::Mode mode = BaseTLB::Read;
428
429 RequestPtr req = new Request(asid, addr, data_size,
430 flags, pc, _cpuId, tid);
431
432 Addr split_addr = roundDown(addr + data_size - 1, block_size);
433 assert(split_addr <= addr || split_addr - addr < block_size);
434
435 // This will need a new way to tell if it's hooked up to a cache or not.
436 if (req->isUncacheable())
437 recordEvent("Uncached Write");
438
435 _status = DTBWaitResponse;
436 if (split_addr > addr) {
437 RequestPtr req1, req2;
438 assert(!req->isLLSC() && !req->isSwap());
439 req->splitOnVaddr(split_addr, req1, req2);
440
441 WholeTranslationState *state =
442 new WholeTranslationState(req, req1, req2, (uint8_t *)(new T),

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456 thread->dtb->translateTiming(req, tc, translation, mode);
457 }
458
459 if (traceData) {
460 traceData->setData(data);
461 traceData->setAddr(addr);
462 }
463
439 _status = DTBWaitResponse;
440 if (split_addr > addr) {
441 RequestPtr req1, req2;
442 assert(!req->isLLSC() && !req->isSwap());
443 req->splitOnVaddr(split_addr, req1, req2);
444
445 WholeTranslationState *state =
446 new WholeTranslationState(req, req1, req2, (uint8_t *)(new T),

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460 thread->dtb->translateTiming(req, tc, translation, mode);
461 }
462
463 if (traceData) {
464 traceData->setData(data);
465 traceData->setAddr(addr);
466 }
467
464 // This will need a new way to tell if it has a dcache attached.
465 if (req->isUncacheable())
466 recordEvent("Uncached Read");
467
468 return NoFault;
469}
470
471#ifndef DOXYGEN_SHOULD_SKIP_THIS
472
473template
474Fault
475TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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505
506template<>
507Fault
508TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
509{
510 return read(addr, *(uint32_t*)&data, flags);
511}
512
468 return NoFault;
469}
470
471#ifndef DOXYGEN_SHOULD_SKIP_THIS
472
473template
474Fault
475TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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505
506template<>
507Fault
508TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
509{
510 return read(addr, *(uint32_t*)&data, flags);
511}
512
513
514template<>
515Fault
516TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
517{
518 return read(addr, (uint32_t&)data, flags);
519}
520
521bool

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550 BaseTLB::Mode mode = BaseTLB::Write;
551
552 RequestPtr req = new Request(asid, addr, data_size,
553 flags, pc, _cpuId, tid);
554
555 Addr split_addr = roundDown(addr + data_size - 1, block_size);
556 assert(split_addr <= addr || split_addr - addr < block_size);
557
513template<>
514Fault
515TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
516{
517 return read(addr, (uint32_t&)data, flags);
518}
519
520bool

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549 BaseTLB::Mode mode = BaseTLB::Write;
550
551 RequestPtr req = new Request(asid, addr, data_size,
552 flags, pc, _cpuId, tid);
553
554 Addr split_addr = roundDown(addr + data_size - 1, block_size);
555 assert(split_addr <= addr || split_addr - addr < block_size);
556
557 // This will need a new way to tell if it's hooked up to a cache or not.
558 if (req->isUncacheable())
559 recordEvent("Uncached Write");
560
558 T *dataP = new T;
559 *dataP = TheISA::htog(data);
560 _status = DTBWaitResponse;
561 if (split_addr > addr) {
562 RequestPtr req1, req2;
563 assert(!req->isLLSC() && !req->isSwap());
564 req->splitOnVaddr(split_addr, req1, req2);
565

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581 thread->dtb->translateTiming(req, tc, translation, mode);
582 }
583
584 if (traceData) {
585 traceData->setAddr(req->getVaddr());
586 traceData->setData(data);
587 }
588
561 T *dataP = new T;
562 *dataP = TheISA::htog(data);
563 _status = DTBWaitResponse;
564 if (split_addr > addr) {
565 RequestPtr req1, req2;
566 assert(!req->isLLSC() && !req->isSwap());
567 req->splitOnVaddr(split_addr, req1, req2);
568

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584 thread->dtb->translateTiming(req, tc, translation, mode);
585 }
586
587 if (traceData) {
588 traceData->setAddr(req->getVaddr());
589 traceData->setData(data);
590 }
591
589 // This will need a new way to tell if it's hooked up to a cache or not.
590 if (req->isUncacheable())
591 recordEvent("Uncached Write");
592
593 // If the write needs to have a fault on the access, consider calling
594 // changeStatus() and changing it to "bad addr write" or something.
595 return NoFault;
596}
597
598
599#ifndef DOXYGEN_SHOULD_SKIP_THIS
600template

--- 484 unchanged lines hidden --- 		592 // If the write needs to have a fault on the access, consider calling
593 // changeStatus() and changing it to "bad addr write" or something.
594 return NoFault;
595}
596
597
598#ifndef DOXYGEN_SHOULD_SKIP_THIS
599template

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