timing.cc (6076:e141cc7896ce) | timing.cc (6102:7fbf97dc6540) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 276 unchanged lines hidden (view full) --- 285 assert(!dcache_pkt); 286 pkt->makeResponse(); 287 completeDataAccess(pkt); 288 } else if (read) { 289 handleReadPacket(pkt); 290 } else { 291 bool do_access = true; // flag to suppress cache access 292 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 276 unchanged lines hidden (view full) --- 285 assert(!dcache_pkt); 286 pkt->makeResponse(); 287 completeDataAccess(pkt); 288 } else if (read) { 289 handleReadPacket(pkt); 290 } else { 291 bool do_access = true; // flag to suppress cache access 292 |
293 if (req->isLlsc()) { | 293 if (req->isLLSC()) { |
294 do_access = TheISA::handleLockedWrite(thread, req); 295 } else if (req->isCondSwap()) { 296 assert(res); 297 req->setExtraData(*res); 298 } 299 300 if (do_access) { 301 dcache_pkt = pkt; --- 77 unchanged lines hidden (view full) --- 379} 380 381void 382TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 383{ 384 MemCmd cmd; 385 if (read) { 386 cmd = MemCmd::ReadReq; | 294 do_access = TheISA::handleLockedWrite(thread, req); 295 } else if (req->isCondSwap()) { 296 assert(res); 297 req->setExtraData(*res); 298 } 299 300 if (do_access) { 301 dcache_pkt = pkt; --- 77 unchanged lines hidden (view full) --- 379} 380 381void 382TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read) 383{ 384 MemCmd cmd; 385 if (read) { 386 cmd = MemCmd::ReadReq; |
387 if (req->isLlsc()) | 387 if (req->isLLSC()) |
388 cmd = MemCmd::LoadLockedReq; 389 } else { 390 cmd = MemCmd::WriteReq; | 388 cmd = MemCmd::LoadLockedReq; 389 } else { 390 cmd = MemCmd::WriteReq; |
391 if (req->isLlsc()) { | 391 if (req->isLLSC()) { |
392 cmd = MemCmd::StoreCondReq; 393 } else if (req->isSwap()) { 394 cmd = MemCmd::SwapReq; 395 } 396 } 397 pkt = new Packet(req, cmd, Packet::Broadcast); 398} 399 --- 47 unchanged lines hidden (view full) --- 447 448 Addr split_addr = roundDown(addr + data_size - 1, block_size); 449 assert(split_addr <= addr || split_addr - addr < block_size); 450 451 452 _status = DTBWaitResponse; 453 if (split_addr > addr) { 454 RequestPtr req1, req2; | 392 cmd = MemCmd::StoreCondReq; 393 } else if (req->isSwap()) { 394 cmd = MemCmd::SwapReq; 395 } 396 } 397 pkt = new Packet(req, cmd, Packet::Broadcast); 398} 399 --- 47 unchanged lines hidden (view full) --- 447 448 Addr split_addr = roundDown(addr + data_size - 1, block_size); 449 assert(split_addr <= addr || split_addr - addr < block_size); 450 451 452 _status = DTBWaitResponse; 453 if (split_addr > addr) { 454 RequestPtr req1, req2; |
455 assert(!req->isLlsc() && !req->isSwap()); | 455 assert(!req->isLLSC() && !req->isSwap()); |
456 req->splitOnVaddr(split_addr, req1, req2); 457 458 typedef SplitDataTranslation::WholeTranslationState WholeState; 459 WholeState *state = new WholeState(req1, req2, req, 460 (uint8_t *)(new T), BaseTLB::Read); 461 thread->dtb->translateTiming(req1, tc, 462 new SplitDataTranslation(this, 0, state), BaseTLB::Read); 463 thread->dtb->translateTiming(req2, tc, --- 102 unchanged lines hidden (view full) --- 566 Addr split_addr = roundDown(addr + data_size - 1, block_size); 567 assert(split_addr <= addr || split_addr - addr < block_size); 568 569 T *dataP = new T; 570 *dataP = TheISA::htog(data); 571 _status = DTBWaitResponse; 572 if (split_addr > addr) { 573 RequestPtr req1, req2; | 456 req->splitOnVaddr(split_addr, req1, req2); 457 458 typedef SplitDataTranslation::WholeTranslationState WholeState; 459 WholeState *state = new WholeState(req1, req2, req, 460 (uint8_t *)(new T), BaseTLB::Read); 461 thread->dtb->translateTiming(req1, tc, 462 new SplitDataTranslation(this, 0, state), BaseTLB::Read); 463 thread->dtb->translateTiming(req2, tc, --- 102 unchanged lines hidden (view full) --- 566 Addr split_addr = roundDown(addr + data_size - 1, block_size); 567 assert(split_addr <= addr || split_addr - addr < block_size); 568 569 T *dataP = new T; 570 *dataP = TheISA::htog(data); 571 _status = DTBWaitResponse; 572 if (split_addr > addr) { 573 RequestPtr req1, req2; |
574 assert(!req->isLlsc() && !req->isSwap()); | 574 assert(!req->isLLSC() && !req->isSwap()); |
575 req->splitOnVaddr(split_addr, req1, req2); 576 577 typedef SplitDataTranslation::WholeTranslationState WholeState; 578 WholeState *state = new WholeState(req1, req2, req, 579 (uint8_t *)dataP, BaseTLB::Write); 580 thread->dtb->translateTiming(req1, tc, 581 new SplitDataTranslation(this, 0, state), BaseTLB::Write); 582 thread->dtb->translateTiming(req2, tc, --- 316 unchanged lines hidden (view full) --- 899 else if (traceData) { 900 // If there was a fault, we shouldn't trace this instruction. 901 delete traceData; 902 traceData = NULL; 903 } 904 905 // the locked flag may be cleared on the response packet, so check 906 // pkt->req and not pkt to see if it was a load-locked | 575 req->splitOnVaddr(split_addr, req1, req2); 576 577 typedef SplitDataTranslation::WholeTranslationState WholeState; 578 WholeState *state = new WholeState(req1, req2, req, 579 (uint8_t *)dataP, BaseTLB::Write); 580 thread->dtb->translateTiming(req1, tc, 581 new SplitDataTranslation(this, 0, state), BaseTLB::Write); 582 thread->dtb->translateTiming(req2, tc, --- 316 unchanged lines hidden (view full) --- 899 else if (traceData) { 900 // If there was a fault, we shouldn't trace this instruction. 901 delete traceData; 902 traceData = NULL; 903 } 904 905 // the locked flag may be cleared on the response packet, so check 906 // pkt->req and not pkt to see if it was a load-locked |
907 if (pkt->isRead() && pkt->req->isLlsc()) { | 907 if (pkt->isRead() && pkt->req->isLLSC()) { |
908 TheISA::handleLockedRead(thread, pkt->req); 909 } 910 911 delete pkt->req; 912 delete pkt; 913 914 postExecute(); 915 --- 149 unchanged lines hidden --- | 908 TheISA::handleLockedRead(thread, pkt->req); 909 } 910 911 delete pkt->req; 912 delete pkt; 913 914 postExecute(); 915 --- 149 unchanged lines hidden --- |